2011 Symposium on VLSI Technology

Format:

Book

Author/Creator:

Institute of Electrical and Electronics Engineers (IEEE), author, issuing body.

Contributor:

IEEE Staff, Contributor.

Language:

English

Subjects (All):

Computers Circuits--Congresses.

Computers Circuits.

Integrated circuits--Very large scale integration--Congresses.

Integrated circuits.

Physical Description:

1 online resource : illustrations

Place of Publication:

[Place of publication not identified] IEEE 2011

Language Note:

English

Summary:

We establish a new record low leakage (JG)-EOT for DRAM compatible MIMcap by further JG reduction to 2×10−8 (10−7) A/cm2 at 0.45 (0.40) nm EOT (0.8 V) using an improved RuOx/TiOx/Sr-rich SrxTiyOz (STO) stack. Further, for the first time we provide insight explaining the origin of the record low JG-EOT achieved, by detailed studies of our TiOx/STO stack on TiN, Ru and RuOx bottom electrodes (BE). TiOx reduces EOT on all BE (without degrading microstructure), but RuOx is needed for low JG. We prove the latter is NOT due to a work function (WF) effect, measuring -on the contrary- strong Fermi Level Pinning (FLP) at STO midgap and same e-injection barrier (∼1.6 eV) from TiN, Ru or RuOx. We determine leakage is controlled by similar traps (∼0.8 eV below CBE) in STO for all stacks and BE, and attribute improvement with RuOx to local STO trap density reduction by eliminating (or even reversing) oxygen scavenging effects near the electrode during crystallization. We demonstrate the potential for further JG reduction by lowering trap density, with theoretical limit for trap-free STO of 10−15 A/cm2 at EOT∼0.4 nm. These results make STO a clear candidate for future DRAM.

Notes:

Bibliographic Level Mode of Issuance: Monograph

ISBN:

9784863481640

4863481640