High-Level Design Validation and Test Workshop, 2006. Eleventh Annual IEEE International / IEEE Computer Society.

Format:

Book

Author/Creator:

IEEE Computer Society, author, issuing body.

Language:

English

Subjects (All):

Computer software--Verification--Congresses.

Computer software.

Electronic circuits--Testing--Congresses.

Electronic circuits.

Physical Description:

1 online resource

Other Title:

2006 IEEE International High Level Design Validation and Test Workshop

Complex Medical Engineering

Place of Publication:

Los Alamitos, CA : IEEE, 2006.

Summary:

A testable implementation of bit parallel multiplier over the finite field GF(2m) is proposed. A function independent test set of length (2m+4), which detects all the single stuck-at faults in an m bit GF(2m) multiplier circuit, is also presented. Test set can be determined readily from the corresponding algebraic forms without running an ATPG tool. The test complexity is lower than ATPG generated or algorithmic test set. The test set provides 100 percent single stuck-at fault coverage. The gate counts of the proposed testable multiplier as a function of degree m has been analyzed. The testable circuit realization requires only two extra inputs for controllability and some additional EX ns and need field testing, built-in self-test (BIST) circuit may be used to generate test pattern internally for detecting faults in the multiplier circuits.

Contents:

Eleventh Annual IEEE International High-Level Design Validation and Test Workshop

Copyright page

Chairs' welcome message

Committees

Table of contents

Session 1: Test Case Generation I

DVGen: Increasing Coverage by Automatically Combining Test Specifications

Test Directive Generation for Functional Coverage Closure Using Inductive Logic Programming

Session 2: Special Session I

Automated Coverage Directed Test Generation Using a Cell-Based Genetic Algorithm

Disjunctive Transition Relation Decomposition for Efficient Reachability Analysis

Trends in Test: Challenges and Techniques

Session 3: Testing and Design for Testability

Formal Verifications in Modern Chip Designs.

Notes:

Description based on publisher supplied metadata and other sources.

ISBN:

9781509091720

1509091726