Performance and tuning considerations for the p690 in a Cluster 1600 / IBM International Technical Support Organization.

Format:

Book

Contributor:

International Business Machines Corporation. International Technical Support Organization.

Series:

IBM redbooks.

Redbooks

Language:

English

Subjects (All):

Database management--Handbooks, manuals, etc.

Database management.

Operating systems (Computers)--Handbooks, manuals, etc.

Operating systems (Computers).

Physical Description:

xvi, 266 p. : ill.

Edition:

1st ed.

Place of Publication:

[White Plains, N.Y.] : IBM Corp. ; [Mountain View, CA] : Vervante [distributor], c2002.

Language Note:

English

Contents:

Front cover

Contents

Figures

Tables

Notices

Trademarks

Preface

The team that wrote this redbook

Become a published author

Comments welcome

Chapter 1. Introduction

Chapter 2. Hardware overview

2.1 What is a Cluster 1600

2.2 The pSeries 690 POWER4 building blocks

2.2.1 The processor subsystem

2.2.2 The memory subsystem

2.2.3 The input/output (I/O) subsystem

2.3 The interconnect fabric

2.3.1 The SP Switch2

2.3.2 The SP Switch2 PCI Attachment Adapter

2.3.3 Internet Protocol (IP) and User Space (US) windows

2.4 Summary

Chapter 3. Features relevant to performance

3.1 Logical partitions (LPARs)

3.1.1 The Hypervisor

3.1.2 LPAR memory overhead

3.1.3 LPAR mode versus Full System Partition mode

3.1.4 LPAR memory and processor allocation

3.2 Affinity logical partitions (ALPARs)

3.3 Technical large page support

3.3.1 Technical large pages and the Virtual Memory Manager (VMM)

3.3.2 Technical large page usage

3.4 Memory affinity

3.4.1 Memory configuration of pSeries 690

3.4.2 Enabling memory affinity

3.4.3 Performance considerations for memory affinity

3.4.4 Memory affinity with technical large page support

3.5 The 32-bit kernel versus the 64-bit kernel

3.5.1 Selecting the 64-bit kernel

3.5.2 The 64-bit application environment

3.6 Application performance tuning

3.6.1 Application tuning guidelines and resources

3.6.2 Compiler considerations

3.6.3 Engineering and Scientific Subroutine Libraries

3.6.4 The Mathematical Acceleration Subsystem (MASS) library

3.6.5 Hostfile considerations for MPI performance

3.6.6 Some final recommendations

3.7 Network connectivity

3.7.1 SP Switch2 PCI Attachment Adapter

3.7.2 EtherChannel configurations

3.7.3 Internet Protocol (IP) and User Space (US) switch windows

3.8 What is next.

Chapter 4. Investigations

4.1 Technical large page investigation

4.1.1 Setting up the environment for technical large page

4.1.2 Creating the Melville MD10 dataset for technical large page

4.1.3 Running the tests for technical large page

4.1.4 Conclusions from the first attempt at technical large page

4.1.5 The second attempt at technical large page

4.1.6 Running both tests again within an affinity LPAR (ALPAR)

4.1.7 Three steps forward, one step back

4.1.8 Memory affinity

4.1.9 Technical large page investigation conclusions

4.2 Tivoli Storage Manager (TSM) investigations

4.2.1 TSM environment without large page

4.2.2 TSM environment with technical large page

4.2.3 TSM and technical large page conclusions

4.2.4 TSM and SP Switch2 communication

4.2.5 TSM and SP Switch2 conclusions

4.3 IP vs. US investigation

4.3.1 Setting up the environment for IP vs. US testing

4.3.2 Running the tests for IP vs. US

4.3.3 IP vs. US on larger LPARs

4.3.4 IP vs. US with different hostfile

4.3.5 IP vs. US with MP_SHARED_MEMORY=yes

4.3.6 IP vs. US with single LPAR using shared memory

4.3.7 IP vs. US investigation conclusions

4.4 CHARMm IP vs. US investigation

4.4.1 Setting up the environment for IP vs. US testing

4.4.2 Running the tests for IP vs. US

4.4.3 CHARMm IP vs. US investigation conclusions

Chapter 5. Summary

Appendix A. Scripts

The pmrinfo tool

The mkllqwcoll tool

The fix_nlspath tool

The mk_temp_dir

The rm_temp_dir

Appendix B. MPI sample programs

The inverse_parallel_enabled.c MPI program

The inverse_parallel.c MPI program

The series_parallel.c MPI program

Appendix C. Parallel tools

PE Benchmarker

MPI Trace

Appendix D. Integrating p690 in an IBM eServer Cluster 1600

IBM eServer pSeries 690

What is an LPAR

What is an HMC.

IBM eServer p690 in a Cluster

CWS, HMC, and p690 functions

The role of the CWS for an attached p690 server

The role of the HMC in a Cluster 1600

Connectivity between CWS, HMC, and p690

Mapping LPAR numbers and node numbers

Planning considerations

Control workstation

Hardware Management Console

IBM eServer p690

Prepare the Hardware Management Console

Software levels

Serial connection

System configuration

Security settings

Domain name of p690 systems

Prepare the p690

Required p690 firmware

Adapter placement for p690

Prepare the control workstation

AIX and PSSP software requirements

Software coexistence

Accessing the Hardware Management Console

Set hardmon authentication

Define switch node numbers

PSSP changes

Hardware monitoring

SPLAN adapter

Additional SDR information

Perspectives

New commands and new command flags

Configuring p690

Adding p690 to a Cluster

Adding p690 LPARs to a Cluster

Deleting LPARs in a Cluster

Adding an Ethernet adapter to an LPAR node

Reconfiguring LPARs

Node numbering

Move or replace the SPLAN adapter

Using multiple LPAR definitions or profiles

Switching between LPAR and Full System Partition mode

Helpful feature codes

Limitations

Example scenarios

CWS with two HMCs and four p690s

One CWS, one HMC, and one p690

CWS, two HMCs, two 9076s, with one p690 and SP Switch2

CWS, HMC, 9076 frame, and p690 with SP Switch

Related publications

IBM Redbooks

Other resources

Referenced Web sites

How to get IBM Redbooks

IBM Redbooks collections

Abbreviations and acronyms

Index

Back cover.

Notes:

"August 2002."

This edition applies to version 3, release 4, of IBM parallel system support program, for use with the IBM AIX operations system version 5 release 1.

Includes bibliographical references (p.245-247) and index.

OCLC:

560375810