IBM eserver zSeries 990 technical guide / [Bill White, Mario Almeida, Dick Jorna].

Format:

Book

Author/Creator:

White, Bill.

Contributor:

Almeida, Mario.

Jorna, Dick.

International Business Machines Corporation. International Technical Support Organization.

Series:

IBM redbooks.

IBM redbooks

Language:

English

Subjects (All):

IBM computers.

Client/server computing.

Physical Description:

1 online resource (284 p.)

Edition:

2nd ed.

Place of Publication:

Poughkeepsie, NY : IBM, International Technical Support Organization, c2004.

Language Note:

English

System Details:

text file

Summary:

The IBM Eserver zSeries® 990 scalable server provides major extensions to the existing zSeries architecture and capabilities. The concept of Logical Channel Subsystems is added, and the maximum number of Processor Units and logical partitions is increased. These extensions provide the base for much larger zSeries servers. This IBM® IBM Redbooks publication is intended for IBM systems engineers, consultants, and customers who need to understand the zSeries 990 features, functions, availability, and services. This publication is part of a series. For a complete understanding of the z990 scalable server capabilities, also refer to our companion Redbooks: IBM Eserver zSeries 990 Technical Introduction, SG24-6863 IBM Eserver zSeries Connectivity Handbook, SG24-5444 Note that the information in this book includes features and functions announced on April 7, 2004, and that certain functionality is not available until hardware Driver Level 55 is installed on the z990 server.

Contents:

Front cover

Contents

Notices

Trademarks

Preface

The team that wrote this redbook

Become a published author

Comments welcome

Chapter 1. zSeries 990 overview

1.1 Introduction

1.2 z990 models

1.3 System functions and features

1.3.1 Processor

1.3.2 Memory

1.3.3 Self-Timed Interconnect (STI)

1.3.4 Channel Subsystem (CSS)

1.3.5 Physical Channel IDs (PCHIDs) and CHPID Mapping Tool

1.3.6 Spanned channels

1.3.7 I/O connectivity

1.3.8 Cryptographic

1.3.9 Parallel Sysplex support

1.3.10 Intelligent Resource Director (IRD)

1.3.11 Hardware consoles

1.3.12 Concurrent upgrades

1.3.13 Performance

1.3.14 Reliability, Availability, and Serviceability (RAS)

1.3.15 Software

1.3.16 Software support

1.3.17 Summary

Chapter 2. System structure and design

2.1 System structure

2.1.1 Book concept

2.1.2 Models

2.1.3 Memory

2.1.4 Ring topology

2.1.5 Connectivity

2.1.6 Frames and cages

2.1.7 The MCM

2.1.8 The PU, SC, and SD chips

2.1.9 Summary

2.2 System design

2.2.1 Design highlights

2.2.2 Book design

2.2.3 Processor Unit design

2.2.4 Processor Unit functions

2.2.5 Memory design

2.2.6 Modes of operation

2.2.7 Model configurations

2.2.8 Storage operations

2.2.9 Reserved storage

2.2.10 LPAR storage granularity

2.2.11 LPAR Dynamic Storage Reconfiguration (DSR)

2.2.12 I/O subsystem

2.2.13 Channel Subsystem

Chapter 3. I/O system structure

3.1 Overview

3.2 I/O cages

3.2.1 Self-Timed Interconnect (STI)

3.2.2 STIs and I/O cage connections

3.2.3 Balancing I/O connections

3.3 I/O and cryptographic feature cards

3.3.1 I/O feature cards

3.3.2 Cryptographic feature cards

3.3.3 Physical Channel IDs (PCHIDs)

3.4 Connectivity

3.4.1 I/O and cryptographic features support and configuration rules.

3.4.2 ESCON channel

3.4.3 FICON channel

3.4.4 OSA-Express adapter

3.4.5 Coupling Facility links

3.4.6 External Time Reference (ETR) feature

3.4.7 Cryptographic features

Chapter 4. Channel Subsystem

4.1 Multiple Logical Channel Subsystem (LCSS)

4.1.1 Logical Channel Subsystem structure

4.1.2 Physical Channel ID (PCHID)

4.1.3 Channel spanning

4.2 LCSS configuration management

4.2.1 z990 configuration management

4.3 LCSS-related numbers

Chapter 5. Cryptography

5.1 Cryptographic function support

5.1.1 Cryptographic Synchronous functions

5.1.2 Cryptographic Asynchronous functions

5.2 z990 Cryptographic processors

5.2.1 CP Assist for Cryptographic Function (CPACF)

5.2.2 PCIX Cryptographic Coprocessor (PCIXCC)

5.2.3 PCI Cryptographic Accelerator (PCICA) feature

5.3 Cryptographic hardware features

5.3.1 PCIX Cryptographic Coprocessor feature

5.3.2 The PCICA feature

5.3.3 Configuration rules

5.3.4 z990 cryptographic feature codes

5.3.5 TKE workstation feature

5.4 Cryptographic features comparison

5.5 Software requirements

Chapter 6. Software support

6.1 Operating system support

6.2 z/OS software support

6.2.1 Compatibility Support for z/OS

6.2.2 Exploitation Support for z/OS

6.2.3 HCD support

6.2.4 Automation changes

6.2.5 SMF support

6.2.6 RMF support

6.2.7 ICKDSF requirements

6.2.8 ICSF support

6.2.9 Additional Exploitation Support considerations

6.3 z/VM software support

6.4 z/VSE and VSE/ESA software support

6.5 TPF software support

6.6 Linux software support

6.7 Summary of software requirements

6.7.1 Summary of z/OS and OS/390 software requirements

6.7.2 Summary of z/VM, z/VSE, VSE/ESA, TPF, and Linux software requirements

6.8 Workload License Charges

6.9 Concurrent upgrades considerations.

Chapter 7. Sysplex functions

7.1 Parallel Sysplex

7.1.1 Parallel Sysplex described

7.1.2 Parallel Sysplex summary

7.2 Sysplex and Coupling Facility considerations

7.2.1 Sysplex configurations and Sysplex Timer considerations

7.2.2 Coupling Facility and CFCC considerations

7.2.3 CFCC enhanced patch apply

7.2.4 Coupling Facility link connectivity

7.2.5 Coupling Facility Resource Manager (CFRM) policy considerations

7.2.6 ICF processor assignments

7.2.7 Dynamic CF dispatching and dynamic ICF expansion

7.3 System-managed CF structure duplexing

7.3.1 Benefits

7.3.2 CF structure duplexing

7.3.3 Configuration planning

7.4 Geographically Dispersed Parallel Sysplex

7.4.1 GDPS/PPRC

7.4.2 GDPS/XRC

7.4.3 GDPS and Capacity Backup (CBU)

7.5 Intelligent Resource Director

7.5.1 LPAR CPU management

7.5.2 Dynamic Channel Path Management

7.5.3 Channel Subsystem Priority Queueing

7.5.4 WLM and Channel Subsystem priority

7.5.5 Special considerations and restrictions

7.5.6 References

Chapter 8. Capacity upgrades

8.1 Concurrent upgrades

8.2 Capacity Upgrade on Demand (CUoD)

8.3 Customer Initiated Upgrade (CIU)

8.4 On/Off Capacity on Demand (On/Off CoD)

8.5 Capacity BackUp (CBU)

8.6 Nondisruptive upgrades

8.6.1 Upgrade scenarios

8.6.2 Planning for nondisruptive upgrades

8.7 Capacity planning considerations

8.7.1 Balanced system design

8.7.2 Superscalar processors

8.7.3 Integrated hardware and system assists

8.8 Capacity measurements

8.8.1 Large Systems Performance Reference (LSPR)

Chapter 9. Environmental requirements

9.1 Introduction

9.1.1 Power and cooling requirements

9.1.2 Power consumption

9.1.3 Internal Battery Feature

9.1.4 Emergency power-off

9.1.5 Cooling requirements

9.2 Weights

9.3 Dimensions.

Appendix A. Hardware Management Console (HMC)

z990 Hardware Management Console

Token ring only wiring scenario

Ethernet only - one-path wiring scenario

Ethernet only - two-path wiring scenario

Token ring and Ethernet wiring scenario

Remote operations

Support Element

z990 HMC enhancements

Appendix B. Fiber optic cabling services

Fiber optic cabling services from IBM

Summary

Glossary

Related publications

IBM Redbooks

Other publications

Online resources

How to get IBM Redbooks

Index

Back cover.

Notes:

"May 2004."

"SC24-6947-01."

The "e" in "eserver" is printed as the symbol for electronic.

Includes bibliographical references and index.

OCLC:

137342291