Advances in analog and RF IC design for wireless communication systems / Gabriele Manganaro, Domine Leenaerts.

Format:

Book

Author/Creator:

Manganaro, G. (Gabriele), 1969-

Contributor:

Leenaerts, Domine M. W.

Language:

English

Subjects (All):

Wireless communication systems.

Physical Description:

x, 300 pages : illustrations ; 25 cm

Edition:

First edition.

Other Title:

Advances in analog and radio-frequency integrated circuit design for wireless communication systems

Place of Publication:

Oxford, UK ; Waltham, MA : Academic Press, 2013.

Summary:

Learn the cutting edge technologies for analog and RF IC design from the experts, This book gives technical introductions to the latest and most significant topics in the area of circuit design of analog/RF ICs for wireless communication systems, with an emphasis on wireless infrastructure. It ranges from very high performance circuits for complex wireless infrastructure systems to selected highly integrated systems for handsets and mobile devices: coverage includes power amplifiers, low noise amplifiers, modulators, analog-to-digital converters (ADCs) and digital-to-analog converters, (DACs), and even single chip radios. Each chapter is authored by renowned experts in the subject and includes a complete introduction, followed by the relevant most significant and recent results on the topic at hand. This book will give researchers in industry and universities a quick grasp of the most important developments in Analog and RF IC design. Key features include: Emerging research topics in RF IC design and its potential application, Case studies and practical implementation examples, The fundamental building blocks of a cellular base station system and satellite infrastructure, Insights from the experts on the design and the technology trade-offs, the challenges and open questions they often face, References to specialist papers for further reading Book jacket.

Contents:

Chapter 1 Wireless Infrastructure 1

Introduction 1

1.1 The cellular infrastructure 2

1.2 The satellite infrastructure 2

1.3 Challenges 3

1.4 This book 5

Conclusive remarks 6

Chapter 2 CMOS Transceivers for Modern Cellular Terminals 7

Introduction 7

2.1 2G transceiver architecture design 7

2.1.1 GSM/EDGE receiver requirement 8

2.1.2 GSM/EDGE transmitter requirement 13

2.2 3/4G transceiver architecture design 20

2.2.1 3G receiver requirements 20

2.2.2 3G transmitter requirements 25

2.2.3 LTE transceiver requirements 27

2.3 Handset calibration 29

2.3.1 Factory calibrations 29

2.3.2 Automatic calibrations 30

Conclusions 31

References 32

Chapter 3 Low-Noise Amplifiers for Cellular Wireless Infrastructure 35

Introduction 35

3.1 LNA specifications 36

3.2 pHEMT-GaAs-based LNAs 36

3.2.1 Single-device LNA .37

3.2.2 Cascode LNA 38

3.2.3 Cascaded LNA 39

3.2.4 MMIC LNA module 40

3.3 Silicon-based LNAs 41

3.3.1 Single-stage BiCMOS LNA 42

3.3.2 Cascaded BiCMOS LNA 44

3.3.3 Broadband BiCMOS LNA 45

3.3.4 CMOS LNAs with sub-1 dB NF 47

Conclusions 49

References 50

Chapter 4 High-Efficiency Power Amplifiers for Wireless Infrastructure 51

Introduction 51

4.1 Wideband Doherty power amplifier 53

4.1.1 Theory of Doherty power amplifiers 53

4.1.2 Circuit realization 61

4.1.3 Simulated and measured results 62

4.2 High-efficiency wideband outphasing power amplifier 64

4.2.1 Wideband class-E Chireix combiner 65

4.2.2 Class-E RF outphasing power amplifier design 67

4.2.3 Experimental results 69

4.3 High-power drivers for high-efficiency RF power amplifiers 71

4.3.1 Driver circuit topology 72

4.3.2 Design and implementation 75

4.3.3 Measurement results 75

References 79

Chapter 5 Digital Fractional-N Frequency Synthesis 83

Introduction 83

5.1 Performance of digital PLLs 87

5.1.1 Noise-power trade-off and spur performance 87

5.1.2 TDC finite resolution in the ADPLL topology 88

5.1.3 TDC finite resolution in the ΔΣ-fractional-N topology 89

5.1.4 Effects of TDC nonlinearity 91

5.2 Techniques for TDC nonlinearity mitigation 92

5.2.1 Element randomization 92

5.2.2 Large-scale dithering 95

5.3 Digital-to-time-converter-based digital PLLs 97

5.3.1 Fractional-N digital PLLs with narrow-range TDCs 97

5.3.2 Digital background correction of DTC nonlinearity 100

5.3.3 Fractional-N digital PLLs with single-bit TDCs 103

5.3.4 Fractional-N divider with unregulated DTC 106

Conclusions 109

References 109

Chapter 6 Mixers and Modulators in Wireless Systems 115

Introduction 115

6.1 Basic principles 115

6.2 Switching mixers 116

6.3 Specifications 117

6.3.1 Gain 117

6.3.2 Linearity 117

6.3.3 Leakage and feedthrough 118

6.3.4 Noise 120

6.4 Single and double balanced mixers 121

6.4.1 Practical implementations 122

6.5 Passive mixers 122

6.6 Passive mixer noise sources 123

6.7 25% Duty cycle passive mixer 126

6.8 Active mixers 128

6.9 Active mixer noise 131

6.10 Active mixer enhancements 133

6.11 Active quadrature mixers 134

6.12 Harmonic rejection mixers 135

Summary remarks 138

References 139

Chapter 7 Integrated Satellite Low Noise Block Down-Converter 141

Introduction 141

7.1 System 142

7.1.1 Configuration 142

7.1.2 LNB block diagram 143

7.1.3 From recommendations toward product specifications 144

7.2 IC technology 149

7.3 Downconverter design 149

7.3.1 Architecture 149

7.3.2 General design considerations 150

7.3.3 Stability considerations 151

7.3.4 Low-noise amplifier 153

7.3.5 Mixer 155

7.3.6 IF amplifier 155

7.4 LO-PLL design 158

7.4.1 Architecture 158

7.4.2 Implementation strategy 159

7.4.3 Noise budget specification 160

7.4.4 LO signal source 161

7.4.5 Frequency divider 163

7.4.6 Phase-frequency detector and charge-pump 165

7.4.7 Charge-pump 166

7.4.8 Crystal oscillator 167

7.5 Experimental results 169

7.6 LNB reference design 171

7.6.1 Design 172

7.6.2 Measurement results 173

References 175

Chapter 8 Bandpass ΔΣ ADCs for Wireless Receivers 177

Introduction 177

8.1 A bandpass ΔΣ primer 179

8.1.1 Discrete-time vs. continuous-time ΔΣ 181

8.1.2 Single bit vs. multi bit 182

8.1.3 Loop-filter architecture: feedback vs. feedforward 182

8.1.4 Single-loop vs. multi-stage architectures 184

8.1.5 Jitter and phase noise 185

8.2 Example bandpass ΔΣ ADC 186

8.2.1 Input LNA and attenuator 187

8.2.2 Loop filter 188

8.2.3 Amplifier 190

8.2.4 Flash ADC 193

8.2.5 Feedback DACs 195

8.3 Experimental results 196

8.3.1 NTF and STF 197

8.3.2 Single-tone and two-tone performance 200

8.3.3 DR vs. F₀ and BW 202

8.3.4 Comparison with other ΔΣ ADCs 202

8.4 Looking forward 204

References 204

Chapter 9 High-performance Pipelined ADCs for Wireless Infrastructure Systems 207

Introduction 207

9.1 Receive path specifications for macro BTS 208

9.2 LF filter and ADC interface 212

9.3 SHA-less front-end design 214

9.4 Switch nonlinearity and digital linearization 218

Summary and future outlook 222

References 222

Chapter 10 Interleaving of Successive-Approximation Register ADCs in Deep Sub-Micron CMOS Technology 225

Introduction 225

10.1 The amalgam of successive-approximation-based data conversion concepts 226

10.2 Bandwidth and noise considerations 228

10.3 Interleaved SAR architecture overview and tradeoffs 231

10.4 Clocking considerations 236

10.5 Interleave mismatches 237

10.6 SAR randomization techniques 242

10.7 Spectral sensing with broadband sampling 243

Summary 245

References 246

Chapter 11 High-Performance Digital-to-Analog Converters for Wireless Infrastructure 251

Introduction 251

11.1 Transmitter architectures 251

11.2 RF DAC design challenges 255

11.2.1 Principle of operation 255

11.2.2 Data capture and pre-processing 260

11.3 Package 262

11.4 Practical design considerations 262

11.5 Measured results 264

11.6 Future direction 266

References 268

Chapter 12 Time-to-Digital Conversion for Digital Frequency Synthesizers 271

Introduction 271

12.1 Background on TDC architectures 274

12.1.1 Vernier technique 274

12.1.2 Interpolation 275

12.1.3 Time-based amplification 276

12.1.4 Oscillator approach 278

12.2 Gated ring oscillator TDC 278

12.2.1 Key concepts 279

12.2.2 High-performance implementation techniques 282

12.2.3 Measured results 284

12.3 Advanced noise shaped TDC architectures 287

12.3.1 Higher-order noise shaping 287

12.3.2 Switched ring oscillator (SRO) TDC 288

12.3.3 Other approaches 289

12.4 TDC implications for type IIPLL topologies 290

Conclusion 291

Acknowledgments 292

References 292.

Notes:

Includes bibliographical references and index.

ISBN:

0123983266

9780123983268

OCLC:

852197642