Computer system design : system-on-chip / Michael J. Flynn, Wayne Luk.

Format:

Book

Author/Creator:

Flynn, M. J. (Michael J.), 1934-

Contributor:

Luk, Wayne.

Samuel P. Orlando Fund.

Language:

English

Subjects (All):

Systems on a chip.

Physical Description:

xx, 334 pages : illustrations ; 25 cm

Place of Publication:

Hoboken, N.J. : Wiley, 2011.

Summary:

"The next generation of computer system designers will be less concerned about details of processors and memories, and more concerned about the elements of a system tailored to particular applications. These designers will have a fundamental knowledge of processors and other elements in the system, but the success of their design will depend on the skills in making system-level tradeoffs that optimize the cost, performance and other attributes to meet application requirements. This book provides a new treatment of computer system design, particularly for System-on-Chip (SOC), which addresses the issues mentioned above. It begins with a global introduction, from the high-level view to the lowest common denominator (the chip itself), then moves on to the three main building blocks of an SOC (processor, memory, and interconnect). Next is an overview of what makes SOC unique (its customization ability and the applications that drive it). The final chapter presents future challenges for system design and SOC possibilities."-- Provided by publisher.

"This book provides a new treatment of computer system design, particularly for System-on-Chip (SOC), which addresses the issues mentioned above"-- Provided by publisher.

Contents:

Machine generated contents note: 1.1.System Architecture: An Overview

1.2.Components of the System: Processors, Memories, and Interconnects

1.3.Hardware and Software: Programmability Versus Performance

1.4.Processor Architectures

1.4.1.Processor: A Functional View

1.4.2.Processor: An Architectural View

1.5.Memory and Addressing

1.5.1.SOC Memory Examples

1.5.2.Addressing: The Architecture of Memory

1.5.3.Memory for SOC Operating System

1.6.System-Level Interconnection

1.6.1.Bus-Based Approach

1.6.2.Network-on-Chip Approach

1.7.An Approach for SOC Design

1.7.1.Requirements and Specifications

1.7.2.Design Iteration

1.8.System Architecture and Complexity

1.9.Product Economics and Implications for SOC

1.9.1.Factors Affecting Product Costs

1.9.2.Modeling Product Economics and Technology Complexity: The Lesson for SOC

1.10.Dealing with Design Complexity

1.10.1.Buying IP

1.10.2.Reconfiguration

1.11.Conclusions

1.12.Problem Set

2.1.Introduction

2.1.1.Design Trade-Offs

2.1.2.Requirements and Specifications

2.2.Cycle Time

2.2.1.Defining a Cycle

2.2.2.Optimum Pipeline

2.2.3.Performance

2.3.Die Area and Cost

2.3.1.Processor Area

2.3.2.Processor Subunits

2.4.Ideal and Practical Scaling

2.5.Power

2.6.Area-Time-Power Trade-Offs in Processor Design

2.6.1.Workstation Processor

2.6.2.Embedded Processor

2.7.Reliability

2.7.1.Dealing with Physical Faults

2.7.2.Error Detection and Correction

2.7.3.Dealing with Manufacturing Faults

2.7.4.Memory and Function Scrubbing

2.8.Configurability

2.8.1.Why Reconfigurable Design?

2.8.2.Area Estimate of Reconfigurable Devices

2.9.Conclusion

2.10.Problem Set

3.1.Introduction

3.2.Processor Selection for SOC

3.2.1.Overview

3.2.2.Example: Soft Processors

3.2.3.Examples: Processor Core Selection

3.3.Basic Concepts in Processor Architecture

3.3.1.Instruction Set

3.3.2.Some Instruction Set Conventions

3.3.3.Branches

3.3.4.Interrupts and Exceptions

3.4.Basic Concepts in Processor Microarchitecture

3.5.Basic Elements in Instruction Handling

3.5.1.The Instruction Decoder and Interlocks

3.5.2.Bypassing

3.5.3.Execution Unit

3.6.Buffers: Minimizing Pipeline Delays

3.6.1.Mean Request Rate Buffers

3.6.2.Buffers Designed for a Fixed or Maximum Request Rate

3.7.Branches: Reducing the Cost of Branches

3.7.1.Branch Target Capture: Branch Target Buffers (BTBs)

3.7.2.Branch Prediction

3.8.More Robust Processors: Vector, Very Long Instruction Word (VLIW), and Superscalar

3.9.Vector Processors and Vector Instruction Extensions

3.9.1.Vector Functional Units

3.10.VLIW Processors

3.11.Superscalar Processors

3.11.1.Data Dependencies

3.11.2.Detecting Instruction Concurrency

3.11.3.A Simple Implementation

3.11.4.Preserving State with Out-of-Order Execution

3.12.Processor Evolution and Two Examples

3.12.1.Soft and Firm Processor Designs: The Processor as IP

3.12.2.High-Performance, Custom-Designed Processors

3.13.Conclusions

3.14.Problem Set

4.1.Introduction

4.2.Overview

4.2.1.SOC External Memory: Flash

4.2.2.SOC Internal Memory: Placement

4.2.3.The Size of Memory

4.3.Scratchpads and Cache Memory

4.4.Basic Notions

4.5.Cache Organization

4.6.Cache Data

4.7.Write Policies

4.8.Strategies for Line Replacement at Miss Time

4.8.1.Fetching a Line

4.8.2.Line Replacement

4.8.3.Cache Environment: Effects of System, Transactions, and Multiprogramming

4.9.Other Types of Cache

4.10.Split I- and D-Caches and the Effect of Code Density

4.11.Multilevel Caches

4.11.1.Limits on Cache Array Size

4.11.2.Evaluating Multilevel Caches

4.11.3.Logical Inclusion

4.12.Virtual-to-Real Translation

4.13.SOC (On-Die) Memory Systems

4.14.Board-based (Off-Die) Memory Systems

4.15.Simple DRAM and the Memory Array

4.15.1.SDRAM and DDR SDRAM

4.15.2.Memory Buffers

4.16.Models of Simple Processor-Memory Interaction

4.16.1.Models of Multiple Simple Processors and Memory

4.16.2.The Strecker-Ravi Model

4.16.3.Interleaved Caches

4.17.Conclusions

4.18.Problem Set

5.1.Introduction

5.2.Overview: Interconnect Architectures

5.3.Bus: Basic Architecture

5.3.1.Arbitration and Protocols

5.3.2.Bus Bridge

5.3.3.Physical Bus Structure

5.3.4.Bus Varieties

5.4.SOC Standard Buses

5.4.1.AMBA

5.4.2.CoreConnect

5.4.3.Bus Interface Units: Bus Sockets and Bus Wrappers

5.5.Analytic Bus Models

5.5.1.Contention and Shared Bus

5.5.2.Simple Bus Model: Without Resubmission

5.5.3.Bus Model with Request Resubmission

5.5.4.Using the Bus Model: Computing the Offered Occupancy

5.5.5.Effect of Bus Transactions and Contention Time

5.6.Beyond the Bus: NOC with Switch Interconnects

5.6.1.Static Networks

5.6.2.Dynamic Networks

5.7.Some NOC Switch Examples

5.7.1.A 2-D Grid Example of Direct Networks

5.7.2.Asynchronous Crossbar Interconnect for Synchronous SOC (Dynamic Network)

5.7.3.Blocking versus Nonblocking

5.8.Layered Architecture and Network Interface Unit

5.8.1.NOC Layered Architecture

5.8.2.NOC and NIU Example

5.8.3.Bus versus NOC

5.9.Evaluating Interconnect Networks

5.9.1.Static versus Dynamic Networks

5.9.2.Comparing Networks: Example

5.10.Conclusions

5.11.Problem Set

6.1.Introduction

6.2.Estimating Effectiveness of Customization

6.3.SOC Customization: An Overview

6.4.Customizing Instruction Processors

6.4.1.Processor Customization Approaches

6.4.2.Architecture Description

6.4.3.Identifying Custom Instructions Automatically

6.5.Reconfigurable Technologies

6.5.1.Reconfigurable Functional Units (FUs)

6.5.2.Reconfigurable Interconnects

6.5.3.Software Configurable Processors

6.6.Mapping Designs Onto Reconfigurable Devices

6.7.Instance-Specific Design

6.8.Customizable Soft Processor: An Example

6.9.Reconfiguration

6.9.1.Reconfiguration Overhead Analysis

6.9.2.Trade-Off Analysis: Reconfigurable Parallelism

6.10.Conclusions

6.11.Problem Set

7.1.Introduction

7.2.SOC Design Approach

7.3.Application Study: AES

7.3.1.AES: Algorithm and Requirements

7.3.2.AES: Design and Evaluation

7.4.Application Study: 3-D Graphics Processors

7.4.1.Analysis: Processing

7.4.2.Analysis: Interconnection

7.4.3.Prototyping

7.5.Application Study: Image Compression

7.5.1.JPEG Compression

7.5.2.Example JPEG System for Digital Still Camera

7.6.Application Study: Video Compression

7.6.1.MPEG and H.26X Video Compression: Requirements

7.6.2.H.264 Acceleration: Designs

7.7.Further Application Studies

7.7.1.MP3 Audio Decoding

7.7.2.Software-Defined Radio with 802.16

7.8.Conclusions

7.9.Problem Set

8.1.Introduction

8.2.Overview

8.3.Technology

8.4.Powering the ASOC

8.5.The Shape of the ASOC

8.6.Computer Module and Memory

8.7.RF or Light Communications

8.7.1.Lasers

8.7.2.RF

8.7.3.Potential for Laser/RF Communications

8.7.4.Networked ASOC

8.8.Sensing

8.8.1.Visual

8.8.2.Audio

8.9.Motion, Flight, and the Fruit Fly

8.10.Motivation

8.11.Overview

8.12.Pre-Deployment

8.13.Post-Deployment

8.13.1.Situation-Specific Optimization

8.13.2.Autonomous Optimization Control

8.14.Roadmap and Challenges

8.15.Summary.

Notes:

Includes bibliographical references and index.

Local Notes:

Acquired for the Penn Libraries with assistance from the Samuel P. Orlando Fund.

ISBN:

0470643366

9780470643365

OCLC:

664666791

Publisher Number:

99949592262