Minimizing and exploiting leakage in VLSI design / by Nikhil Jayakumar ... [and others].

Format:

Book

Contributor:

Jayakumar, Nikhil.

Language:

English

Subjects (All):

Integrated circuits--Very large scale integration--Design.

Integrated circuits.

Integrated circuits--Very large scale integration.

Physical Description:

xxvii, 214 pages : illustrations ; 24 cm

Place of Publication:

New York ; London : Springer, 2010.

Summary:

Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs.

This book presents techniques aimed at reducing and exploiting leakage power in digital VLSI ICs. The first part of this book presents several approaches to reduce leakage in a circuit. The second part of this book shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic, with adaptive body bias to make the designs robust to variations. The third part of this book presents designs and implementation details of a sub-threshold logic, with adaptive body bias to make the designs robust to variations. The third part of this book presents design and implementation details of a sub-threshold IC, using the ideas presented in the second part of this book.

Provides a variety a approaches to control and exploit leakage, including implicit approaches to find the leakage of all input vectors in a design, techniques to find the minimum leakage vector of a design (with and without circuit modification), ASIC approaches to drastically reduce leakage, and methods to find the optimal reverse bias voltage to maximally reduce leakage.

Presents a variation-tolerant, practical design methodology to implement sub-threshold logic using closed-loop adaptive body bias (ABB) and Network of PLA (NPLA) based design. In addition, asynchronous micropipelining techniques are presented, to substantially reclaim the speed penalty of sub-threshold design.

Validates the proposed ABB and NPLA sub-threshold design approach by implementing a BFSK transmitter design in the proposed design style. Test results from the fabricated IC are provided as well, indicating that a power improvement of 20X can be obtained for a 0.25um process (projected power improvements are 100X to 500X for 65nm processes).

Contents:

1 Introduction 1

1.1 The Need for Low Power Design 1

1.2 Leakage and Its Contribution to IC Power Consumption 2

1.3 Summary 5

References 6

Part I Leakage Reduction Techniques: Minimizing Leakage in Modem Day DSM Processes

2 Existing Leakage Minimization Approaches 9

2.1 Leakage Minimization Approaches: An Overview 9

2.1.1 Power Gating/MTCMOS 9

2.1.2 Body Biasing/VTCMOS 10

2.1.3 Input Vector Control 11

2.2 Summary 12

References 13

3 Computing Leakage Current Distributions 15

3.1 Overview 15

3.2 Introduction 15

3.3 Background 17

3.3.1 Reduced Ordered Binary Decision Diagrams 17

3.3.2 Algebraic Decision Diagrams 19

3.4 The Intuition Behind Our Approach 21

3.5 Related Previous Work 22

3.6 Our Approach 22

3.6.1 Exact Computation of the Leakages of All Vectors 22

3.6.2 Approximate Computation of Leakages of All Vectors 25

3.7 Experimental Results 27

3.8 Summary 30

References 31

4 Finding a Minimal Leakage Vector in the Presence of Random PVT Variations Using Signal Probabilities 33

4.1 Overview 33

4.2 Introduction 34

4.3 The Intuition Behind Our Approach 35

4.4 Related Previous Work 36

4.5 Our Approach 38

4.5.1 Computing Signal Probabilities 39

4.5.2 Finding the Best Leakage Candidate 41

4.5.3 Finding Best Leakage State for Selected Gate 41

4.5.4 Accepting Leakage States and Final MLV Determination 43

4.6 Experimental Results 45

4.6.1 Selecting Parameter Values for MLVC and MLVC-VAR 45

4.6.2 Comparing MLVC with Existing Techniques 46

4.6.3 Comparing MLVC-VAR with MLVC and RVA 49

4.7 Summary 52

References 53

5 The HL Approach: A Low-Leakage ASIC Design Methodology 55

5.1 Overview 55

5.2 Philosophy of the HL Approach 56

5.3 Related Previous Work 56

5.4 The HL Approach 57

5.4.1 Design Methodology 59

5.4.2 Advantages and Disadvantages of the HL Approach 60

5.5 Experimental Results 62

5.5.1 Comparison of Placed and Routed Circuits 63

5.6 Using Gate Length Biasing Instead of VT Change 68

5.7 Leakage Reduction in Domino Logic 71

5.8 Summary 74

References 76

6 Simultaneous Input Vector Control and Circuit Modification 77

6.1 Overview 77

6.2 Introduction 77

6.3 The Intuition Behind Our Approach 78

6.4 Related Previous Work 79

6.5 Our Approach 80

6.5.1 The Gate Replacement Algorithm 82

6.6 Experimental Results 84

6.7 Summary 89

References 90

7 Optimum Reverse Body Biasing for Leakage Minimization 91

7.1 Overview 91

7.2 Goal and Background 92

7.3 Related Previous Work 94

7.4 Leakage Monitoring/Self-Adjusting Scheme 96

7.4.1 Leakage Current Monitoring Block (LCM) 96

7.4.2 Digital Control Block 98

7.5 Summary 99

References 99

8 Part I: Conclusions and Future Directions 101

References 104

Part II Practical Methodologies for Sub-threshold Circuit Design: Exploiting Leakage Through Sub-threshold Circuit Design

9 Exploiting Leakage: Sub-threshold Circuit Design 109

9.1 Overview 109

9.2 Introduction 109

9.2.1 The Opportunity 111

9.3 Summary 113

References 113

10 Adaptive Body Biasing to Compensate for PVT Variations 115

10.1 Overview 115

10.2 Related Previous Work 115

10.3 Preliminaries: PLAs 116

10.3.1 PLA Design 116

10.3.2 PLA Operation 117

10.4 The Adaptive Body Biasing Solution 118

10.4.1 Self-Adjusting Bulk-Bias Circuit 120

10.5 Experimental Results 122

10.6 Loop Gain of the Adaptive Body Biasing Loop 124

10.7 Summary 126

References 127

11 Optimum VDD for Minimum Energy 129

11.1 Overview 129

11.2 Introduction 129

11.3 Related Previous Work 130

11.4 Preliminaries 131

11.4.1 Operation of the PLA 131

11.4.2 Some Definitions 132

11.5 Experiments 133

11.5.1 Energy Estimation for a Circuit of PLAs 137

11.6 Summary 141

References 141

12 Reclaiming the Sub-threshold Speed Penalty Through Micropipelining 143

12.1 Overview 143

12.2 Our Approach 144

12.2.1 Asynchronous Micropipelined NPLAs 144

12.2.2 Synthesis of Micropipelined PLA Networks 147

12.2.3 Circuit Details of PLAs and Stutter Blocks 148

12.3 Experimental Results 151

12.4 Optimum VDD for Micropipelined NPLAs 152

12.5 Summary 154

References 155

13 Part II: Conclusions and Future Directions 157

References 159

Part III Design of a Sub-threshold BFSK Transmitter IC

14 Design of the Chip 163

14.1 Overview 163

14.2 Test Vehicle 163

14.2.1 BFSK Radio Transmitter Architecture 164

14.3 System Architecture 165

14.3.1 PLA Basics 165

14.3.2 Network of PLA Operation 166

14.3.3 Dynamic Compensation Circuit 167

14.3.4 The Digital BFSK Modulator 168

14.3.5 Digital to Analog Converter 170

14.3.6 Common Source Amplifier 171

14.3.7 Antenna 172

14.4 Design Specifications 172

14.4.1 Link Budget Analysis 172

14.5 Summary 174

References 175

15 Implementation of the Chip 177

15.1 Overview 177

15.2 Design Flow 177

15.3 HDL to Netlist Flow 179

15.4 SPICE Verification of Dynamic Compensation 180

15.5 DAC and Amplifier Design 181

15.6 Special Considerations 183

15.6.1 Testability and Redundancy 183

15.6.2 Voltage Domains 184

15.7 Standard Cell-Based BFSK Design 185

15.8 IO Pad and ESD Diode Design 185

15.9 Chip Integration and Pin-out 186

15.10 Layout 188

15.11 Summary of Verification Methodologies 190

15.12 Summary 190

References 190

16 Experimental Results 193

16.3 Overview 193

16.2 Functional Verification 193

16.3 Dynamic Compensation Circuit 193

16.4 Operating Ranges 196

16.5 Spectrum of Output Sinusoidal Signals 197

16.6 Comparison with Standard Cells 197

16.7 Summary 199

Reference 199.

Notes:

Includes index.

ISBN:

9781441909497

1441909494

OCLC:

440121772