13th Asian Test Symposium : proceedings. Kenting, Taiwan, November 15-17, 2004 / IEEE Computer Society.

Format:

Book

Conference/Event

Contributor:

IEEE Xplore (Online service)

IEEE Computer Society.

Conference Name:

Asian Test Symposium (13th : 20034 : Kenting, Taiwan)

Language:

English

Subjects (All):

Electronic digital computers--Circuits--Testing--Congresses.

Electronic digital computers.

Electronic digital computers--Circuits--Testing.

Electronic circuits--Testing--Congresses.

Electronic circuits.

Fault-tolerant computing--Congresses.

Fault-tolerant computing.

Electronic circuits--Testing.

Genre:

Conference papers and proceedings.

Physical Description:

xxvi, 465 pages : illustrations

Other Title:

ATS'04

Test Symposium, 2004, 13th Asian.

Place of Publication:

Los Alamitos, Calif. : IEEE Computer Society, [2004]

System Details:

Mode of access: World Wide Web.

text file

Contents:

Session A1 SOC Testing / Chair: Erik Larsson

Multi-frequency Test Access Mechanism Design for Modular SOC Testing / Q. Xu, N. Nicolici 2

Rapid and Energy-Efficient Testing for Embedded Cores / Y. Han, Y. Hu, H. Li, X. Li, A. Chandra 8

Constructing Transparency Paths for IP Cores Using Greedy Searching Strategy / J. Xing, H. Wang, S. Yang 14

Adding Testability to an Asynchronous Interconnect for GALS SoC / A. Efthymiou, J. Bainbridge, D. Edwards 20

Session B1 Low-Power Testing / Chair: Chien-Mo James Li

Test Power Reduction with Multiple Capture Orders / K.-J. Lee, S.-J. Hsu, C.-M. Ho 26

Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths / Z. You, K. Yamaguchi, M. Inoue, J. Savir, H. Fujiwara 32

Low Power BIST with Smoother and Scan-Chain Reorder / N.-C. Lai, Y.-H. Fu, S.-J. Wang 40

Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction / Y. Higami, S. Kajihara, S. Kobayashi, Y. Takamatsu 46

Session C1 Analog BIST / Chair: Michel Renovell

A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters / H.-W. Ting, B.-D. Liu, S.-J. Chang 52

A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC / G.-X. Chen, C.-L. Lee, J.-E. Chen 58

A [Sigma - Delta] Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose / H.-C. Hong, C.-W. Wu, K.-T. Cheng 62

A Built-In Loopback Test Methodology for RF Transceiver Circuits Using Embedded Sensor Circuits / S. Bhattacharya, A. Chatterjee 68

Session A2 Advanced DFT / Chair: Der-Chen Huang

Multiple Scan Tree Design with Test Vector Modification / K. Miyase, S. Kajihara, S. Reddy 76

An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains / J.-C. Rau, C.-H. Lin, J.-Y. Chang 82

Scan-Based BIST Using an Improved Scan Forest Architecture / D. Xiang, M.-J. Chen, K.-W. Li, Y.-L. Wu 88

The Efficient Multiple Scan Chain Architecture Reducing Power Dissipation and Test Time / I.-S. Lee, T. Ambler, Y.M. Hur 94

Session B2 Fault Analysis / Chair: Yoshinobu Higami

Testing for Missing-Gate Faults in Reversible Circuits / J.P. Hayes, I. Polian, B. Becker 100

Properties of Maximally Dominating Faults / I. Pomeranz, S. Reddy 106

I[subscript DDQ] Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment / M. Hashizume, D. Yoneda, H. Yotsuyanagi, T. Tada, T. Koyama, I. Morita, T. Tamesada 112

High Level Fault Injection for Attack Simulation in Smart Cards / K. Rothbart, U. Neffe, C. Steger, R. Weiss, E. Rieger, A. Muhlberger 118

Session C2 Cross-Talk Testing / Chair: Hiroshi Takahashi

Efficient Identification of Crosstalk Induced Slowdown Targets / S. Nazarian, S. Gupta, M. Breuer 124

Modeling and Testing Crosstalk Faults in Inter-Core Interconnects that Include Tri-State and Bi-Directional Nets / W. Sirisaengtaksin, S. Gupta 132

A New Path Delay Test Scheme Based on Path Delay Inertia / C.-L. Chen, C.-L. Lee, M.-S. Wu 140

A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI / K. S.-M. Li, C.-L. Lee, C.-C. Su, J.-E. Chen 145

Session A3 Functional Testing / Chair: Debesh K. Das

Efficient Template Generation for Instruction-Based Self-Test of Processor Cores / K. Kambe, M. Inoue, H. Fujiwara 152

Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores / S. Shamshiri, H. Esmaeilzadeh, Z. Navabi 158

A Snapshot Method to Provide Full Visibility for Functional Debugging Using FPGA / C.-L. Chuang, D.-J. Lu, C.-N. Liu 164

A Systematic Way of Functional Testing for VLSI Chips / S. Xu 170

Session B3 Logic BIST / Chair: Kiyoshi Furuya

Weighted Pseudo-Random BIST for N-detection of Single Stuck-at Faults / C. Yu, S. Reddy, I. Pomeranz 178

A BIST Approach to On-Line Monitoring of Digital VLSI Circuits: A CAD Tool / S. Biswas, S. Mukhopadhyay, A. Patra 184

Seed Selection Procedure for LFSR-Based BIST with Multiple Scan Chains and Phase Shifters / M. Arai, H. Kurokawa, K. Ichino, S. Fukumoto, K. Iwasaki 190

Nonlinear CA Based Design of Test Set Generator Targeting Pseudo-Random Pattern Resistant Faults / S. Das, A. Kundu, B. Sikdar 196

Session C3 Fault Diagnosis / Chair: Shyue-Kung Lu

Compactor Independent Direct Diagnosis / W.-T. Cheng, K.-H. Tsai, Y. Huang, N. Tamarapalli, J. Rajski 204

Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits / S. Ghosh, K.-W. Lai, W.-B. Jone, S.-C. Chang 210

Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set / H. Takahashi, Y. Yamamoto, Y. Higami, Y. Takamatsu 216

Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests / Y. Sato, H. Takahashi, Y. Higami, Y. Takamatsu 222

Session A4 SOC Test Scheduling / Chair: Chih-Tsun Huang

Hybrid BIST Test Scheduling Based on Defect Probabilities / Z. He, G. Jervan, Z. Peng, P. Eles 230

Pair Balance-Based Test Scheduling for SOCs / Y. Hu, Y.-H. Han, H.-W. Li, T. Lv, X.-W. Li 236

RAIN (RAndom Insertion) Scheduling Algorithm for SoC Test / J. Im, S. Chun, G. Kim, J. An, S. Kang 242

March Based Memory Core Test Scheduling for SOC / W.-L. Wang 248

An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint / S. Edbom, E. Larsson 254

Session B4 Memory Testing / Chair: Wu-Tung Cheng

On Test and Diagnostics of Flash Memories / C.-T. Huang, J.-C. Yeh, Y.-Y. Shih, R.-F. Huang, C.-W. Wu 260

Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution / L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, S. Borri, M. Hage-Hassan 266

A Measurement Unit for Input Signal Analysis of SRAM Sense Amplifier / Y.-M. Sheng, M.-J. Hsiao, T.-Y. Chang 272

An Efficient Diagnosis Scheme for Random Access Memories / J.-F. Li, C.-D. Huang 277

Evaluation of Intra-Word Faults in Word-Oriented RAMs / S. Hamdioui, J. Reyes, Z. Al-Ars 283

Session C4 Analog Testing / Chair: Soon-Jyh

Low-Cost Analog Signal Generation Using a Pulse-Density Modulated Digital ATE Channel / J. Rivoir 290

A Low-Cost Diagnosis Methodology for Pipelined A/D Converters / C.-H. Huang, K.-J. Lee, S.-J. Chang 296

Reconfiguration for Enhanced ALternate Test (REAL Test) of Analog Circuits / G. Srinivasan, S. Goyal, A. Chatterjee 302

Dynamic Analog Testing via ATE Digital Test Channels / C.-C. Su, C.-S. Chang, H.-W. Huang, D.-S. Tu, C.-L. Lee, J.C.-H. Lin 308

Session A5 Testable Design / Chair: Shiyu Xu

Design and Implementation of Self-Testable Full Range Window Comparator / M. Wong, Y. Zhang 314

Efficient Test Methodologies for Conditional Sum Adders / J.-F. Li, C.-C. Hsu 319

A Novel Approach for On-line Testable Reversible Logic Circuit Design / D.-P. Vasudevan, P. Lala, J. Parkerson 325

Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores / S. Das, B. Sikdar, P. Chaudhuri 331

Session B5 Testability Analysis / Chair: Ching-Hwa Cheng

Circuit-Width Based Heuristic for Boolean Reasoning / G. Li, X. Li 336

Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity / D. Das, T. Inoue, S. Chakraborty, H. Fujiwara 342

Classification of Sequential Circuits Based on [tau]k Notation / C. Ooi, H. Fujiwara 348

A New Way of Detecting Reconvergent Fanout Branch Pairs in Logic Circuits / E. Edirisuriya, S. Xu 354

Session C5 Yield and Reliability / Chair: Jwu-E Chen

Burn-In Stress Test of Analog CMOS ICs / C.-L. Wey, M.-Y. Liu 360

Fail Pattern Identification for Memory Built-In Self-Repair / R.-F. Huang, C.-L. Su, C.-W. Wu, S.-T. Lin, K.-L. Luo, Y.-J. Chang 366

Reduce Yield Loss in Delay Defect Detection in Slack Interval / H. Yan, A. Singh 372

Considering Fault Dependency and Debugging Time Lag in Reliability Growth Modeling during Software Testing / C.-Y. Huang, C.-T. Lin, C.-C. Sue 378

Session A6 Fault Tolerance / Chair: Xiaowei Li

Intelligible Test Techniques to Support Error-Tolerance / M. Breuer 386

Bounding Rollback-Recovery of Large Distributed Computation in WAN Environment / J.-M. Yang, D.-F. Zhang 394

Full Restoration of Multiple Faults in WDM Networks without Wavelength Conversion / C.-C. Sue, J.-Y. Yeh, C.-Y. Huang 400

On Improvement in Fault Tolerance of Hopfield Neural Networks / N. Kamiura, T. Isokawa, N. Matsui 406

Session B6 FPGA Testing and Test Reduction / Chair: Terumine Hayashi

Testing and Diagnosis Techniques for LUT-Based FPGA's / S.-K. Lu, H.-C. Wu, S.-J. Yan, Y.-C. Tsai 414

Device Resizing Based Optimization of Analog Circuits for Reduced Test Cost: Cost Metric and Case Study / D. Han, A. Chatterjee 420

A Test Decompression Scheme for Variable-Length Coding / H. Ichihara, M. Ochi, M. Shintani, T. Inoue 426

Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test / Y. Shi, S. Kimura, N. Togawa, M. Yanagisawa, T. Ohtsuki 432

Session C6 Delay Testing / Chair: Kazumi Hatayama

Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-chip Interconnects / L. Wang, S. Gupta, M. Breuer 440

A Postprocessing Procedure of Test Enrichment for Path Delay Faults / I. Pomeranz, S. Reddy 448

Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing / H.-F. Ko, N. Nicolici 454

Analysis and Attenuation Proposal in Ground Bounce / A. Zenteno, V. Champac, M. Renovell, F. Azais 460.

Notes:

"IEEE Computer Society Order Number P2235"--T.p. verso.

Includes bibliographical references and author index.

ISBN:

0769522351

9780769522357

OCLC:

57180851

Access Restriction:

Restricted for use by site license.