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ETS 2004. Ninth IEEE European Test Symposium : proceedings : 23-26 May, 2004, Corsica, France / [sponsored by IEEE Computer Society TTTC, LIRMM].
- Format:
- Book
- Conference/Event
- Conference Name:
- IEEE European Test Symposium (9th : 2004 : Corsica, France)
- Language:
- English
- Subjects (All):
- Integrated circuits--Testing--Congresses.
- Integrated circuits.
- Genre:
- Conference papers and proceedings.
- Physical Description:
- xiv, 181 pages : illustrations, portraits
- Other Title:
- Test Symposium, 2004, ETS 2004, proceedings, Ninth IEEE European.
- Former Title:
- IEEE European Test Workshop
- Place of Publication:
- Los Alamitos, Calif. : IEEE Computer Society Press, [2004]
- System Details:
- Mode of access: World Wide Web.
- text file
- Contents:
- Debug and Diagnosis
- At-Speed On-Chip Diagnosis of Board-Level Interconnect Faults / A. Jutman 2
- Analog Measurement Techniques
- Accurate Tap-Delay Measurements Using a Differential Oscillation Technique / O. Petre, H. Kerkhoff 10
- Delay Chain Based Programmable Jitter Generator / T. Xia, P. Song, K. Jenkins, J.-C. Lo 16
- Design for Dependability
- Application of Local Design-for-Reliability Techniques for Reducing Wear-out Degradation of CMOS Combinational Logic Circuits / X. Xuan, A. Chatterjee, A. Singh 24
- A New Self-Checking Multiplier by Use of a Code-Disjoint Sum-Bit Duplicated Adder / D. Marienfeld, E. Sogomonyan, V. Ocheretnij, M. Gossel 30
- ATE Hardware and Software
- Software Development for an Open Architecture Test System / B. Parnas, A. Pramanick, M. Elston, T. Adachi 38
- Timing and Delay Testing
- Delay Fault Testing and Silicon Debug Using Scan Chains / R. Datta, A. Sebastine, J. Abraham 46
- Manufacturing-Oriented Testing of Delay Faults in the Logic Architecture of Symmetrical FPGAs / P. Girard, O. Heron, S. Pravossoudovitch, M. Renovell 52
- MEMS Testing
- Electrically-Induced Thermal Stimuli for MEMS Testing / N. Dumas, F. Azais, L. Latorre, P. Nouet 60
- MEMS Built
- In-Self-Test Using MLS / A. Dhayni, S. Mir, L. Rufer 66
- Test Planning and Test Resource Optimization for Droplet-Based Microfluidic Systems / F. Su, S. Ozev, K. Chakrabarty 72
- Embedded Core Testing
- User-Constrained Test Architecture Design for Modular SOC Testing / L. Krundel, S. Goel, E. Marinissen, M.-L. Flottes, B. Rouzeyre 80
- Pipelined Test of SOC Cores through Test Data Transformations / O. Sinanoglu, A. Orailoglu 86
- Test Resource Partitioning
- Relating Entropy Theory to Test Data Compression / K. Balakrishnan, N. Touba 94
- A Compression-Driven Test Access Mechanism Design Approach / P. Gonciari, B. Al-Hashimi 100
- Fault Simulation and Verification
- Enhanced 3-Valued Logic/Fault Simulation for Full Scan Circuits Using Implicit Logic Values / S. Kajihara, K. Saluja, S. Reddy 108
- Signal Integrity Verification Using High Speed Monitors / V. Avendano, V. Champac, J. Figueras 114
- Analog BIST
- Towards a BIST Technique for Noise Figure Evaluation / M. Negreiros, L. Carro, A. Susin 122
- A New BIST Scheme for 5GHz Low Noise Amplifiers / J.-Y. Ryu, B. Kim, I. Sylla 127
- All-Pass SC Biquad Reconfiguration Scheme for Oscillation Based Analog BIST / U. Kac, F. Novak 133
- Memory Testing
- Dynamic Read Destructive Fault in Embedded-SRAMs: Analysis and March Test Solution / L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, S. Borri, M. Hage-Hassan 140
- Tests for Address Decoder Delay Faults in RAMs Due to Inter-gate Opens / A. van de Goor, S. Hamdioui, Z. Al-Ars 146
- ATPG and High-Level Test
- Functional Fault Coverage: The Chamber of Secrets or an Accurate Estimation of Gate-Level Coverage? / F. Fummi, C. Marconcini, G. Pravadelli 154
- Automatic Test Pattern Generation for Resistive Bridging Faults / P. Engelke, I. Polian, M. Renovell, B. Becker 160
- Advances in DfT
- A Design Methodology to Realize Delay Testable Controllers Using State Transition Information / T. Iwagaki, S. Ohtake, H. Fujiwara 168
- An Efficient Scan Tree Design for Test Time Reduction / Y. Bonhomme, T. Yoneda, H. Fujiwara, P. Girard 174.
- Notes:
- Previous conferences entitled: European Test Workshop.
- "IEEE Computer Society Order Number P2119"--T.p. verso.
- Includes bibliographical references and author index.
- ISBN:
- 0769521193
- 9780769521190
- OCLC:
- 56673696
- Access Restriction:
- Restricted for use by site license.
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