FCCM 2004. 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines : proceedings : 20-23 April, 2004, Napa, California / sponsored by IEEE Computer Society Technical Committee on Computer Architecture ; [edited by Jeffrey Arnold and Kenneth L. Pocek].

Format:

Book

Conference/Event

Contributor:

Pocek, Kenneth L.

Arnold, Jeffrey M.

IEEE Xplore (Online service)

IEEE Computer Society. Technical Committee on Computer Architecture.

Conference Name:

FCCM (Symposium) (12th : 2004 : Napa, Calif.)

Language:

English

Subjects (All):

Field programmable gate arrays--Congresses.

Field programmable gate arrays.

Computer engineering--Congresses.

Computer engineering.

Genre:

Conference papers and proceedings.

Physical Description:

x, 346 pages : illustrations

Other Title:

12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

IEEE Symposium on Field-Programmable Custom Computing Machines

Proceedings, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

Place of Publication:

Los Alamitos, Calif. : IEEE Computer Society, [2004]

System Details:

Mode of access: World Wide Web.

text file

Contents:

Session 1 Architecture

Time-Critical Software Deceleration in an FCCM / P. James-Roxby, G. Brebner, D. Bemmann 3

Design Patterns for Reconfigurable Computing / A. DeHon, J. Adams, M. DeLorimier, N. Kapre, Y. Matsuda, H. Naeimi, M. Vanier, M. Wrighton 13

Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor / M. Vuletic, L. Pozzi, P. Ienne 24

Session 2 Tools I

Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs / D. Zaretsky, G. Mittal, X. Tang, P. Banerjee 37

PyGen: A MATLAB/Simulink Based Tool for Synthesizing Parameterized and Energy Efficient Designs Using FPGAs / J. Ou, V. K. Prasanna 47

Session 3 Arithmetic I

Automated Least-Significant Bit Datapath Optimization for FPGAs / M. L. Chang, S. Hauck 59

An Arithmetic Library and Its Application to the N-Body Problem / K. H. Tsoi, C. H. Ho, H. C. Yeung, P. H. W. Leong 68

Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs / A. A. Gaffar, O. Mencer, W. Luk, P. Y. K. Cheung 79

Session 4 Communications Applications

A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder / J. Liang, R. Tessier, D. Goeckel 91

A Flexible Hardware Encoder for Low-Density Parity-Check Codes / D.-U. Lee, W. Luk, C. Wang, C. Jones, M. Smith, J. Villasenor 101

Session 5 Networking I

ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers / R. Krishnamurthy, S. Yalamanchili, K. Schwan, R. West 115

Deep Packet Filter with Dedicated Logic and Read Only Memories / Y. H. Cho, W. H. Mangione-Smith 125

A Methodology for Synthesis of Efficient Intrusion Detection Systems on FPGAs / Z. K. Baker, V. K. Prasanna 135

Session 6 Applications I

Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-Time Applications / M. Leeser, S. Miller, H. Yu 147

FPGA-Based Acceleration of the 3D Finite-Difference Time-Domain Method / J. P. Durbano, F. E. Ortiz, J. R. Humphrey, P. F. Curt, D. W. Prather 156

Session 7 Tools II

Register Binding for FPGAs with Embedded Memory / H. Al Atat, I. Ouaiss 167

Defect and Fault Tolerance for Reconfigurable Molecular Computing / M. B. Tahoori, S. Mitra 176

Communications Scheduling for Concurrent Processes on Reconfigurable Computers / M. Gokhale, C. Ahrens, J. Frigo, C. Wolinski 186

Session 8 Applications II

Reconfigurable Molecular Dynamics Simulator / N. Azizi, I. Kuon, A. Egier, A. Darabiha, P. Chow 197

Accelerating Seismic Migration Using FPGA-Based Coprocessor Platform / C. He, M. Lu, C. Sun 207

Session 9 Arithmetic II

Closing the Gap: CPU and FPGA Trends in Sustainable Floating-Point BLAS Performance / K. D. Underwood, K. S. Hemmert 219

FPGA-Based Implementation of a Robust IEEE-754 Exponential Unit / C. C. Doss, R. L. Riley, Jr. 229

Design of an On-Line IEEE Floating-Point Addition Unit for FPGAs / S. D. Krueger, P.-M. Seidel 239

Session 10 Networking II

Scalable Pattern Matching for High Speed Networks / C. R. Clark, D. E. Schimmel 249

Pre-decoded CAMs for Efficient and High-Speed NIDS Pattern Matching / I. Sourdis, D. Pnevmatikatos 258

A Structured System Methodology for FPGA Based System-on-a-Chip Design / P. Sedcole, P. Y. K. Cheung, G. Constantinides, W. Luk 271

Fine-tuning Loop-Level Parallelism for Increasing Performance of DSP Applications on FPGAs / E. Ozer, A. P. Nisbet, D. Gregg 273

Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path / M. D. Galanis, G. Theodoridis, S. Tragoudas, D. Soudris, C. E. Goutis 275

Hardware-in-the-Loop Evolution of a 3-Bit Multiplier / G. V. Larchev, J. D. Lohn 277

FPGA Montgomery Multiplier Architectures

A Comparison / C. McIvor, M. McLoone, J. V. McCanny 279

Design Methodology of a Configurable System-on-Chip Architecture / S. Wallner 283

Word-Length Optimization of Folded Polynomial Evaluation / G. A. Constantinides, A. Miah, N. Sidahao 285

Migrating Functionality from ROMs to Embedded Multipliers / G. W. Morris, G. A. Constantinides, P. Y. K. Cheung 287

A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-Level Computation / D. Wentzlaff, A. Agarwal 289

Validation of an Advanced Encryption Standard (AES) IP Core / V. Tomashau, T. Kean 291

Unidirectional Switch-Boxes for Synthesizable Reconfigurable Arrays / S. Khawam, T. Arslan, F. Westall 293

The MOLEN Processor Prototype / G. Kuzmanov, G. Gaydadjiev, S. Vassiliadis 296

FPGA Acceleration of Rigid Molecule Interactions / T. Van Court, Y. Gu, M. C. Herbordt 300

A Single Program Multiple Data Parallel Processing Platform for FPGAs / P. James-Roxby, P. Schumacher, C. Ross 302

Hyperreconfigurable Architectures for Fast Run Time Reconfiguration / S. Lange, M. Middendorf 304

A Generator of High-Speed Floating-Point Modules / G. Leyva, G. Caffarena, C. Carreras, O. Nieto-Taladriz 306

A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA / A. Hodjat, I. Verbauwhede 308

An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding / W. J. Gross, F. R. Kschischang, P. G. Gulak 310

Buffer Schemes for Runtime Reconfiguration of Function Variants in Communication Systems / D. Eilers, H. Steckenbiller, A. Herkersdorf 312

FPGA Based Network Intrusion Detection Using Content Addressable Memories / L. Bu, J. A. Chandy 316

Using FIFOs in Hardware-Software Co-design for FPGA Based Embedded Systems / C. Ross, W. Bohm 318

A Reconfigurable SoC Architecture and Caching Scheme for 3D Medical Image Processing / J. Li, C. Papachristou, R. Shekhar 320

Implementation Results of Bloom Filters for String Matching / M. Attig, S. Dharmapurikar, J. Lockwood 322

An FPGA Implementation for a High Throughput Adaptive Filter Using Distributed Arithmetic / D. J. Allred, W. Huang, V. Krishnan, H. Yoo, D. V. Anderson 324

Power Management for FPGAs: Power-Driven Design Partitioning / R. Mukherjee, S. O. Memik 326

Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor / N. Suzuki, S. Kurotaki, M. Suzuki, N. Kaneko, Y. Yamada, K. Deguchi, Y. Hasegawa, H. Amano, K. Anjo, M. Motomura, K. Wakabayashi, T. Toi, T. Awashima 328

FPGA Based Embedded Processing Architecture for the QRD-RLS Algorithm / D. Boppana, K. Dhanoa, J. Kempa 330

A Dataflow Control Unit for C-to-Configurable Pipelines Compilation Flow / A. Cappelli, A. Lodi, C. Mucci, M. Toma, F. Campi 332

Secure Remote Control of Field-Programmable Network Devices / H. Song, J. Lu, J. Lockwood, J. Moscola 334

An Alternate Wire Database for Xilinx FPGAs / N. Steiner, P. Athanas 336

Duty Cycle Aware Application Design Using FPGAs / S. Mohanty, V. K. Prasanna 338

Automating the Layout of Reconfigurable Subsystems via Template Reduction / S. Phillips, A. Sharma, S. Hauck 340

Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine / M. Dyer, M. Platzner, L. Thiele 342.

Notes:

"IEEE Computer Society Order Number P2230"--T.p. verso.

Includes bibliographical references and author index.

ISBN:

0769522300

9780769522302

OCLC:

56828210

Access Restriction:

Restricted for use by site license.