15th IEEE International Conference on Application-Specific Systems, Architectures and Processors. proceedings : September 2-29, 2004, Galveston, Texas / IEEE Computer Society.

Format:

Book

Conference/Event

Contributor:

IEEE Xplore (Online service)

IEEE Computer Society.

Conference Name:

International Conference on Application-Specific Systems, Architectures, and Processors (15th : 2004 : Galveston, Tex.)

Language:

English

Subjects (All):

Array processors--Congresses.

Array processors.

Signal processing--Digital techniques--Congresses.

Signal processing.

Signal processing--Digital techniques.

Application-specific integrated circuits--Congresses.

Application-specific integrated circuits.

Genre:

Conference papers and proceedings.

Physical Description:

x, 412 pages : illustrations

Other Title:

Fifteenth IEEE International Conference on Application-Specific Systems, Architectures and Processors

Application specific systems, architectures, and processors

Half t.p. title: ASAP 2004

Place of Publication:

Los Alamitos, Calif. : IEEE Computer Society, [2004]

System Details:

Mode of access: World Wide Web.

text file

Contents:

Defect-Tolerant Molecular Electronics / P. Kuekes 2

Session 1 Scheduling and Codesign

Modeling and Scheduling Parallel Data Flow Systems Using Structured Systems of Recurrence Equations / F. Charot, M. Nyamsi, P. Quinton, C. Wagner 6

Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals / F. Hannig, J. Teich 17

CHARMED: A Multi-objective Co-synthesis Framework for Multi-mode Embedded Systems / V. Kianzad, S. Bhattacharyya 28

Reliability-Aware Co-synthesis for Embedded Systems / Y. Xie, L. Li, M. Kandemir, N. Vijaykrishnan, M. Irwin 41

Session 2 Arithmetic I

Complex Square Root with Operand Prescaling / M. Ercegovac, J. Muller 52

Parallel Montgomery Multipliers / M. Sanu, E. Swartzlander, Jr., C. Chase 63

Improved-Throughput Networks of Basic On-line Arithmetic Modules for DSP Applications / A. Tenca, A. Shantilal, M. Sinky 73

Decimal Floating-Point Division Using Newton-Raphson Iteration / L. Wang, M. Schulte 84

Session 3 Instruction Set Extensions

A Public-key Cryptographic Processor for RSA and ECC / H. Eberle, N. Gura, S. Shantz, V. Gupta, L. Rarick, S. Sundaram 98

Architectural Support for Arithmetic in Optimal Extension Fields / J. Grossschadl, S. Kumar, C. Paar 111

Evaluating Instruction Set Extensions for Fast Arithmetic on Binary Finite Fields / A. Fiskiran, R. Lee 125

Efficient Processing of Color Image Sequences Using a Color-Aware Instruction Set on Mobile Systems / J. Kim, D. Wills 137

Session 4 (Special) Nanocomputing / Chair: Jose Fortes

Binary Multiplication Based on Single Electron Tunneling / C. Lageweg, S. Cotofana, S. Vassiliadis 152

A Novel Highly Reliable Low-Power Nano Architecture When von Neumann Augments Kolmogorov / V. Beiu 167

Session 5 Microarchitecture, Compilers and Optimization

Register Organization for Enhanced On-Chip Parallelism / R. Sangireddy 180

Design and Evaluation of a Network-Based Asynchronous Architecture for Cryptographic Devices / L. Dilparic, D. Arvind 191

Common Subexpression Elimination Involving Multiple Variables for Linear DSP Synthesis / A. Hosangadi, F. Fallah, R. Kastner 202

Optimizing the Memory Bandwidth with Loop Morphing / J. Gomez, P. Marchal, S. Verdoorlaege, L. Pinuel, F. Catthoor 213

Switching-Activity Minimization on Instruction-level Loop Scheduling for VLIW DSP Applications / Z. Shao, Q. Zhuge, M. Liu, B. Xiao, E. Sha 224

Session 6 Arithmetic II

A Digit-Serial Algorithm for the Discrete Logarithm Modulo 2[superscript k] / A. Fit-Florea, D. Matula 236

An Algorithm and Hardware Architecture for Integrated Modular Division and Multiplication in GF(p) and GF(2[superscript n]) / L. Tawalbeh, A. Tenca 247

Detecting Faults in Four Symmetric Key Block Ciphers / L. Breveglieri, I. Koren, P. Maistri 258

A Low-Power Carry Skip Adder with Fast Saturation / M. Schulte, K. Chirca, J. Glossner, H. Wang, S. Mamidi, P. Balzola, S. Vassiliadis 269

Session 7 Communication, Interfaces and Memory

A Hierarchical Classification Scheme to Derive Interprocess Communication in Process Networks / A. Turjan, B. Kienhuis, E. Deprettere 282

Efficient On-Chip Communications for Data-Flow IPs / A. Fraboulet, T. Risset 293

Automatic Synthesis of Customized Local Memories for Multicluster Application Accelerators / M. Kudlur, K. Fan, M. Chu, S. Mahlke 304

Optimized Data-Reuse in Processor Arrays / S. Siegel, R. Merker 315

Session 8 (Special) Reconfigurable Computing / Chair: Oskar Mencer

Hyper-Programmable Architectures for Adaptable Networked Systems / G. Brebner, P. James-Roxby, E. Keller, C. Kulkarni 328

Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing / M. Vuletic, L. Pozzi, P. Ienne 339

Session 9 Applications

Families of FPGA-Based Algorithms for Approximate String Matching / T. Van Court, M. Herbordt 354

Biosequence Similarity Search on the Mercury System / P. Krishnamurthy, J. Buhler, R. Chamberlain, M. Franklin, K. Gyang, J. Lancaster 365

Stride Permutation Networks for Array Processors / T. Jarvinen, P. Salmela, H. Sorokin, J. Takala 376

A Packet Scheduling Algorithm for IPSec Multi-Accelerator Based Systems / F. Castanier, A. Ferrante, V. Piuri 387

Design of the QBIC Wearable Computing Platform / O. Amft, M. Lauffer, S. Ossevoort, F. Macaluso, P. Lukowicz, G. Troster 398.

Notes:

"IEEE Computer Society Order Number P2226"--T.p. verso.

Includes bibliographical references and author index.

ISBN:

0769522262

9780769522265

OCLC:

56718644

Access Restriction:

Restricted for use by site license.