10th International Symposium on Asynchronous Circuits and Systems. proceedings : 19-23 April, Crete, Greece / sponsored by IEEE Computer Society Technical Committee on VLSI ... [and others].

Format:

Book

Conference/Event

Contributor:

IEEE Xplore (Online service)

IEEE Computer Society. Technical Committee on VLSI.

Conference Name:

International Symposium on Advanced Research in Asynchronous Circuits and Systems (10th : 2004 : Crete, Greece)

Language:

English

Subjects (All):

Asynchronous circuits--Congresses.

Asynchronous circuits.

Computers, Pipeline--Congresses.

Computers, Pipeline.

Embedded computer systems--Congresses.

Embedded computer systems.

Genre:

Conference papers and proceedings.

Physical Description:

xii, 251 pages : illustrations

Other Title:

Half t.p. title: ASYNC 2004

Asynchronous circuits and systems

Place of Publication:

Los Alamitos, Calif. : IEEE Computer Society Press, [2004]

System Details:

Mode of access: World Wide Web.

text file

Contents:

Synchronous Latency Insensitive Design / Prof. Christer Svensson 3

Session I Design and Test / Chair: Montek Singh

A Fast and Energy-Efficient Stack / J. Ebergen, D. Finchelstein, R. Kao, J. Lexau, D. Hopkins 7

Static Tokens: Using Dataflow to Automate Concurrent Pipeline Synthesis / J. Teifel, R. Manohar 17

General Testers for Asynchronous Circuits / R. Negulescu 28

Session II Timing / Chair: Supratik Chakraborty

Analog Micropipeline Rings for High Precision Timing / S. Fairbanks, S. Moore 41

Transistor Sizing: How to Control the Speed and Energy Consumption of a Circuit / J. Ebergen, J. Gainsley, P. Cunningham 51

Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model / M. Imai, M. Ozcan, T. Nanya 62

Session III Asynchronous Designs I / Chair: Steve Furber

Non-Uniform Access Asynchronous Register Files / D. Fang, R. Manohar 75

Phase Alignment Using Asynchronous State Machines / A. Kaviani 86

High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells / M. Ferretti, R. Ozdag, P. Beerel 95

Contacting Biological Cells with Electronic Circuits / Dr. Martin Jenkner 109

Session IV Synthesis and Verification / Chair: Mark Josephs

Bolstering Faith in GasP Circuits through Formal Verification / X. Kong, R. Negulescu 113

A General Purpose Behavioural Asynchronous Synthesis System / M. Sacker, A. Brown, P. Wilson, A. Rushton 125

Synthesis of Speed Independent Circuits Based on Decomposition / T. Yoneda, H. Onda, C. Myers 135

Session V Synchronization / Chair: Alex Yakovlev

Handshake Protocols for De-Synchronization / I. Blunno, J. Cortadella, A. Kondratyev, L. Lavagno, K. Lwin, C. Sotiriou 149

Hiding Synchronization Delays in a GALS Processor Microarchitecture / G. Semeraro, D. Albonesi, G. Magklis, M. Scott, S. Dropsho, S. Dwarkadas 159

Data Synchronization Issues in GALS SoCs / R. Dobkin, R. Ginosar, C. Sotiriou 170

Bringing Handshake Technology to the Open Market / Ad Peeters 183

Session VI Asynchronous Design II / Chair: Doug Edwards

A Channel Based Asynchronous Low Power High Performance Standard-Cell Based Sequential Decoder Implemented with QDI Templates / R. Ozdag, P. Beerel 187

Asynchronous FIR Filters: Towards a New Digital Processing Chain / F. Aeschlimann, E. Allier, L. Fesquet, M. Renaudin 198

An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm / A. Efthymiou, W. Suntiamorntut, J. Garside, L. Brackenbury 207

Session VII High Speed and Pulse Logic / Chair: Jens Sparso

High-Speed Reduced Stack Dual Lock Circuits / N. Saadallah, X. Kong, R. Negulescu 219

An Eight-bit Divider Implemented in Asynchronous Pulse Logic / M. Nystrom, E. Ou, A. Martin 229

Long Wires and Asynchronous Control / R. Ho, J. Gainsley, R. Drost 240.

Notes:

"IEEE Computer Society Order Number P2133"--T.p. verso.

Includes bibliographical references and author index.

ISBN:

0769521339

9780769521336

OCLC:

55073870

Access Restriction:

Restricted for use by site license.