IOLTS 2004. 10th IEEE International On-Line Testing Symposium : proceedings : 12-14 July, 2004, Funchal, Madeira Island, Portugal / edited by C. Metra ... [and others] ; sponsored by IEEE Computer Society Test Technology Technical Council.

Format:

Book

Conference/Event

Contributor:

Metra, C. (Cecilia)

IEEE Xplore (Online service)

IEEE Computer Society. Technical Council on Test Technology.

Conference Name:

IEEE International On-Line Testing Symposium (10th : 2004 : Funchal, Madeira Island, Portugal)

Language:

English

Subjects (All):

Electronic circuits--Testing--Congresses.

Electronic circuits.

Online data processing--Congresses.

Online data processing.

Electronic circuit design--Congresses.

Electronic circuit design.

Error-correcting codes (Information theory)--Congresses.

Error-correcting codes (Information theory).

Electronic circuits--Testing.

Genre:

Conference papers and proceedings.

Physical Description:

xii, 252 pages : illustrations

Other Title:

International On-Line Testing Sumposium

On-Line Testing Symposium, 2004, IOLTS 2004, proceedings, 10th IEEE International.

Place of Publication:

Los Alamitos, Calif. : IEEE Computer Society, [2004]

System Details:

Mode of access: World Wide Web.

text file

Contents:

Opening Session

Keynote Talk / Moderator: Y. Zorian

A Pragmatic Approach to On-Line Testing / V. Agarwal 1

Session 1 Timing and Transient Faults / Moderator: J. Abraham

Modeling and Simulation of Time Domain Faults in Digital Systems / D. Barros Junior, F. Vargas, M. B. Santos, I. C. Teixeira, J. P. Teixeira 5

Sizing CMOS Circuits for Increased Transient Error Tolerance / Y. S. Dhillon, A. U. Diril, A. Chatterjee, A. D. Singh 11

Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop / J. M. Cazeaux, M. Omana, C. Metra 17

Session 2 Self Testing and Self Checking Circuits / Moderator: R. Stefanelli

Necessary and Sufficient Conditions for the Existence of Totally Self-Checking Circuits / V. Saposhnikov, Vl. Saposhnikov, A. Morozov, M. Gossel 25

Self-Checking Code-Disjoint Carry-Select Adder with Low Area Overhead by Use of Add1-Circuits / V. Ocheretnij, D. Marienfeld, E. S. Sogomonyan, M. Gossel 31

A Hierarchical Self Test Scheme for SoCs / C. Kretzschmar, C. Galke, H. T. Vierhaus 37

Session 3 Checker and Voter Design / Moderator: Y. Savaria

Single-Output Embedded Checkers for Systematic Unordered Codes / S. Tarnick 45

A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations / A. Rao, T. Haniotakis, Y. Tsiatouhas, V. Kaky 52

New High Speed CMOS Self-Checking Voter / J. M. Cazeaux, D. Rossi, C. Metra 58

Session 4 Concurrent Error Detection / Moderator: M. Abadir

Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory Blocks / A. Krasniewski 67

Low Cost On-Line Testing of RF Circuits / M. Negreiros, L. Carro, A. A. Susin 73

Hybrid Soft Error Detection by Means of Infrastructure IP Cores / L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante 79

Panel Session 1 On Emerging Field Reliability and Dependability Challenges / Organizer: Y. Zorian

Session 5 Microprocessor On-Line Testing / Moderator: J. Hayes

A Comparative Study of the Design of Synchronous and Asynchronous Self-Checking RISC Processors / P. D. Hyde, G. Russell 89

Testing of Hard Faults in Simultaneous Multithreaded Processors / E. F. Weglarz, K. K. Saluja, T. M. Mak 95

Fault Detection Enhancement in Cache Memories Using a High Performance Placement Algorithm / H. R. Zarandi, S. G. Miremadi, H. Sarbazi-Azad 101

Session 6 On-Line Testing Evaluation / Moderator: R. Velazco

Transient Fault Emulation of Hardened Circuits in FPGA Platforms / M. Garcia-Valderas, C. Lopez-Ongil, M. Portela-Garcia, L. Entrena-Arrontes 109

On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs / P. Bernardi, M. Sonza Reorda, L. Sterpone, M. Violante 115

Asynchronous Circuits Sensitivity to Fault Injection / Y. Monnet, M. Renaudin, R. Leveugle 121

Session 7 Error Correcting Code Based Fault Tolerance / Moderator: J. Karlsson

Designing a High Speed Decoder for Cyclic Codes / A. M'Sir, F. Monteiro, A. Dandache, B. Lepley 129

Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems / D. Rossi, A. Muccio, A. K. Nieuwland, A. Katoch, C. Metra 135

A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities / G. C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, A. Salsano 141

Session 8 Reconfiguration, Repair, and Reuse for Fault Tolerance / Moderator: A. Salsano

A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies / A. Agarwal, B. C. Paul, K. Roy 149

Scrubbing Away Transients and Jiggling around the Permanent: Long Survival of FPGA Systems through Evolutionary Self-Repair / M. Garvie, A. Thompson 155

Hardware Reconfiguration Scheme for High Availability Systems / C. Metra, A. Ferrari, M. Omana, A. Pagni 161

Operating System Function Reuse to Achieve Low-Cost Fault Tolerance / M. Portolan, R. Leveugle 167

A New Code with Reduced EMI and Partial EC Possibilities / E. Bohl, M. Bohl, E. Dilger 175

A Matlab Based On-Chip Signal Generation and Analysis Environment for Mixed Signal Circuits / T. O'Shea, I. Grout 176

Automated Logic SER Analysis and On-Line SER Reduction / A. K. Nieuwland, P. Gindner 177

On the Design of Long-Life Reliable Systems for Ground-Based Applications / J. M. Vieira dos Santos 178

On-Line Monitoring Capabilities of Oscillation Test Techniques: Results Demonstration in an OTA / R. Picos, M. Roca, E. Isern, S. A. Bota, E. Garcia 179

An Intrinsically Robust Technique for Fault Tolerance under Multiple Upsets / C. A. L. Lisboa, L. Carro 180

Survey of the Algorithms in the Column-Matching BIST Method / P. Fiser, H. Kubatova 181

A Technique to Reduce Power and Test Application Time in BIST / D. Ghosh, S. Bhunia, K. Roy 182

Optimization of the Theory of FDD of DES for Alleviation of the State Explosion Problem and Development of CAD Tools for On-Line Testing of Digital VLSI Circuits / S. Biswas, S. Mukhopadhyay, A. Patra 184

Session 10 Built In Self Test / Moderator: H.-J. Wunderlich

BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs / P. Girard, O. Heron, S. Pravossoudovitch, M. Renovell 187

Accumulator Based Test-per-Scan BIST / P. Karpodinis, D. Kagaris, D. Nikolos 193

A BIST-Based Charge Analysis for Embedded Memories / B. Alorda, V. Canals, I. de Paul, J. Segura 199

Session 11 Safety and Security / Moderator: D. Gizopoulos

A System for Fault Detection and Reconfiguration of Hardware Based Active Networks / N. G. Bartzoudis, A. G. Fragkiadakis, D. J. Parish, J. L. Nunez 207

Fault Tolerant Mechatronics / E. Dilger, R. Karrelmeyer, B. Straube 214

Scan Design and Secure Chip / D. Hely, M.-L. Flottes, F. Bancel, B. Rouzeyre, N. Berard, M. Renovell 219

Session 12 Dependability Evaluation / Moderator: E. Simeu

On Combining Fault Classification and Error Propagation Analysis in RT-Level Dependability Evaluation / A. Ammari, K. Hadjiat, R. Leveugle 227

Performance Evaluation and Failure Rate Prediction for the Soft Implemented Error Detection Technique / B. Nicolescu, Y. Savaria, R. Velazco 233

Experimental Evaluation of Master/Checker Architecture Using Power Supply- and Software-Based Fault Injection / A. Rajabzadeh, S. G. Miremadi, M. Mohandespour 239

Panel Session 2 Reliability Implications of Statistical Design / Organizer: R. Aitken.

Notes:

Some conferences previously entitled: IEEE International On-Line Testing Workshop.

"IEEE Computer Society Order Number P2180"--T.p. verso.

Includes bibliographical references and author index.

ISBN:

0769521800

9780769521800

OCLC:

56112970

Access Restriction:

Restricted for use by site license.

Online:

Table of contents only