Proceedings. 17th International Conference on VLSI Design, concurrently with the 3rd International Conference on Embedded Systems Design, 5-9 January, 2004, Mumbai, India / technical co-sponsorship IEEE Circuits and Systems Society, IEEE Electron Devices Society ; sponsored by VLSI Society of India, Ministry of Information and Communication Technologies ; in cooperation with ACM-SIGDA.

Format:

Book

Conference/Event

Contributor:

IEEE Xplore (Online service)

IEEE Circuits and Systems Society.

IEEE Electron Devices Society.

VLSI Society of India.

India. Ministry of Communications and Information Technology.

Conference Name:

International Conference on VLSI Design (17th : 2004 : Mumbai, India)

International Conference on Embedded Systems Design (3rd : 2004 : Mumbai, India)

Language:

English

Subjects (All):

Integrated circuits--Very large scale integration--Design and construction--Congresses.

Integrated circuits.

Integrated circuits--Very large scale integration--Design and construction.

Signal processing--Digital techniques--Congresses.

Signal processing.

Signal processing--Digital techniques.

Electronic digital computers--Circuits--Congresses.

Electronic digital computers.

Electronic digital computers--Circuits.

Genre:

Conference papers and proceedings.

Physical Description:

xxxv, 1095 pages : illustrations

Other Title:

Proceedings on VLSI Design 2004 : design methodologies for the gigascale era

VLSI Design 2004

Design methodologies for the gigascale era

VLSI Design, 2004, proceedings, 17th International Conference on.

Place of Publication:

Los Alamitos, Calif. : IEEE Computer Society Press, [2004]

System Details:

Mode of access: World Wide Web.

text file

Contents:

Technology CAD: Technology Modeling, Device Design and Simulation / S. Saha, B. Gadepally 3

Physical Design Trends and Layout-Based Fault Modeling / S. Sur-Kolay, P. Dasgupta, B. Bhattacharya, S. Zachariah 6

High Level Design Validation: Current Practices and Future Directions / I. Ghosh, R. Mukherjee, M. Prasad, M. Fujita 9

System Software for Embedded Applications / K. Ramamritham, K. Arya, G. Fohler 12

Design Challenges in Sub-100nm High Performance Microprocessors / S. Narendra, V. Erraguntla, J. Tschanz, N. Borkar 15

Bridging the Gap between Asynchronous Design and Designers / P. Beerel, J. Cortadella, A. Kondratyev 18

Embedded Test for Low Cost Manufacturing / J. Rajski, N. Mukherjee, J. Tyszer, T. Rinderknecht 21

Synchronous Methodology for Designing Hardware, Software and Mixed Embedded Systems / G. Berry 24

High Speed Integrated A to D Converters / P. Jespers 29

CMOS Scaling for Sub-90 nm to Sub-10 nm / H. Iwai 30

Session 1A Low Voltage Analog Design

Techniques for Very Low-Voltage Operation of Continuous-Time Analog CMOS Circuits / J. Ramirez-Angulo, R. Gonzalez-Carvajal, A. Lopez-Martin 39

Comparative Study of Low Voltage OTA Designs / D. Majumdar 47

Design of Amplifier with Rail-to-Rail CMR with 1V Power Supply / S. Mitra, A. Chandorkar 52

Design of Low Voltage Low Power CMOS OP-Amps with Rail-to-Rail Input/Output Swing / S. Gopalaiah, A. Shivaprasad, S. Panigrahi 57

Session 1B Low Power Logic Synthesis

Modeling and Estimation of Leakage in Sub-90nm Devices / A. Raychowdhury, S. Mukhopadhyay, K. Roy 65

Energy-aware Logic Synthesis and Technology Mapping for MUX-Based FPGAs / M. Marik, A. Pal 73

Low Power Combinational Circuit Synthesis Targeting Multiplexer Based FPGAs / D. Satyanarayana, S. Chattopadhyay, J. Sasidhar 79

Synthesis of Low Power High Performance Dual-VT PTL Circuits / D. Samanta, A. Pal 85

Session 1C Formal Verification

Formal Verification of C Language Based VLSI Designs / M. Fujita 93

Formal Verification of Modules under Real Time Environment Constraints / A. Banerjee, P. Dasgupta, P. Chakrabarti 103

Property Refinement Techniques for Enhancing Coverage of Formal Property Verification / P. Basu, P. Dasgupta, P. Chakrabarti, C. Mohan 109

Towards the Complete Elimination of Gate/Switch Level Simulations / N. Krishnamurthy, J. Bhadra, M. Abadir, J. Abraham 115

Session 1D Embedded System Design

Tiniest Web Server / H. Shrikumar

On Design and Implementation of an Embedded Automatic Speech Recognition System / S. Phadke, R. Limaye, S. Verma, K. Subrarmanian 127

Embedded Hardware Face Detection / T. Theocharides, G. Link, N. Vijaykrishnan, M. Irwin, W. Wolf 133

Session 2A Mixed Signal Design

Algorithmic Macromodelling Methods for Mixed-Signal Systems / J. Roychowdhury 141

An Element Rotation Algorithm for Multi-bit DAC Nonlinearities in Complex Bandpass [Delta Sigma]AD Modulators / H. San, H. Kobayashi, S. Kawakami, N. Kuroiwa 151

Error Correction in Pipelined ADCs Using Arbitrary Radix Calibration / A. Savla, J. Leonard, A. Ravindran 157

A 2.5GHz CMOS Fully-Integrated [Delta Sigma]-Controlled Fractional-N Frequency Synthesizer / R. Dehghani 163

A Switch-Cap Regulator for SoC Applications / N. Bansal, A. Katyal 168

Session 2B Design Methodology

Automated Architectural Optimization of Digital FIR Filters / R. Mehler, D. Zhou 177

Partial Tag Comparison: A New Technology for Power-Efficient Set-Associative Cache Designs / R. Min, Z. Xu, Y. Hu, W.-b. Jone 183

Bridge over Troubled Wrappers: Automatic Interface Synthesis / V. D'silva, S. Ramesh, A. Sowmya 189

Gate Sizing and Buffer Insertion Using Economic Models for Power Optimization / A. Murugavel, N. Ranganathan 195

Charge-Sharing-Problem Reduced Split-Path Domino Logic / S.-S. Yoon, S.-R. Yoon, S.-W. Kim, C. Kim 201

Session 2C Leakage Reduction

Low Energy Switch Block for FPGAs / R. Krishnan, J. de Gyvez 209

Leakage Reduction Techniques in a 0.13um SRAM Cell / S. Natarajan, S. Romanovsky, A. Achyuthan, W. Leung 215

Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies / G. Yang, Z. Wang, S.-M. Kang 222

A New Technique for Leakage Reduction in CMOS Circuits Using Self-Controlled Stacked Transistors / N. Hanchate, N. Ranganathan 228

Analysis and Optimization of Enhanced MTCMOS Scheme / R. Rao, J. Burns, R. Brown 234

Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic / K. Chopra, S. Vrudhula, S. Bhardwaj 240

Session 2D Embedded OS and Software

New Frontiers for Embedded Computing / V. Yodaiken 249

An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures / K. Srinivasan, K. Chatha 255

Energy-Optimizing Source Code Transformations for OS-driven Embedded Software / Y. Fei, S. Ravi, A. Raghunathan, N. Jha 261

Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization / W. Wang, A. Raghunathan, N. Jha 267

Session 3A VLSI Technology

Technological Challenges of Advanced CMOS Processing and Their Impact on Design Aspects / C. Claeyes 275

Response Surface Modeling of 100nm CMOS Process Technology Using Design of Experiment / H. Srinivasaiah, N. Bhat 285

Screening of Hot Electron Effect during Plasma Processing / P. Srinivasan, B. Vootukuru, D. Misra 291

Session 3B Reconfigurable Design

Designing Reconfigurable Systems in Lava / S. Singh 299

Configurable Platforms with Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips / K. Sekar, K. Lahiri, S. Dey 307

Session 3C Design Tools

Assertion Based Verification Using HDVL / K. Datta, P. Das 319

Design and Implementation of a Parallel Verilog Simulator: PVSim / T. Li, Y. Guo, S.-K. Li 329

Energy Profiler for Hardware/Software Co-design / R. Sreeramaneni, S. Vrudhula 335

Session 3D Emerging Areas in VLSI

A Tutorial on the Emerging Nanotechnology Devices / T. Raja, V. Agrawal, M. Bushnell 343

Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes / D. Wentzloff, B. Calhoun, R. Min, A. Wang, N. Ickes, A. Chandrakasan 361

Which new Design Methodologies are required for the Giga Scale Era?

A Vision for the Broadband Network / B. Witowsky 373

A System Approach to Energy Management / D. Monticelli 377

Design for Verification with SystemVerilog / P. Moorby 378

Session 4A RF Design

A 800 MHz System-on-Chip for Wireless Infrastructure Applications / S. Agarwala, P. Wiley, A. Rajagopal, A. Hill, R. Damodaran, L. Nardini, T. Anderson, S. Mullinnix, J. Flores, H. Yue, A. Chachad, J. Apostol, K. Castille, U. Narasimha, T. Wolf, N. Nagaraj, M. Krishnan, L. Nguyen, T. Kroeger, M. Gill, P. Groves, B. Webster, J. Graber, C. Karlovich 381

A Low Voltage, Low Noise CMOS RF Receiver Front-End / J. Long, R. Weber 393

Design of RF Tuner for Cable Modem Applications / V. Babu, S. Seth, A. Chandorkar 398

Design and Implementation of 935 MHz FM Transceiver for Radio Telemetry and 2.45 GHz Direct AQPSK Transmitter in CMOS / A. Ghosh, B. Perumana, A. Dutta, P. Sen, Y. Kumar, V. Garg, T. Bhattacharyaya, N. Chakrabarti 404

Design of Power Amplifiers at 2.4 GHz/900 MHz and Implementation of On-chip Linearization Technique in 0.18/0.25[mu]m CMOS / P. Sen, V. Garg, R. Garg, N. Chakrabarti 410

Design, Analysis, and Implementation of Analog Complex Filter for Low-IF Wireless LAN Application / T. Teo, E.-S. Khoo, D. Uday, C.-B. Tear 416

Session 4B Interconnect

Interconnect Modeling for Copper/Low-k Technologies / N. Nagaraj, T. Bonifield, A. Singh, R. Griesmer, P. Balsara 425

Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling / P. Gupta, A. Kahng 431

Static Timing Analysis of Irreversible Crosstalk Noise Pulse Faults / M. Phadoongsidhi, K. Saluja 437

A Bus Encoding Technique for Power and Cross-Talk Minimization / P. Subrahmanya, R. Manimegalai, V. Kamakoti, M. Mutyam 443

Intra-Bus Crosstalk Estimation Using Word-Level Statistics / S. Gupta, S. Katkoori 449

On Buffering Schemes for Long Multi-layer Nets / V. Prasad, M. Desai 455

Session 4C Fault Detection

On-Chip Testing of Embedded Transducers / S. Mir, L. Rufer, B. Courtois 463

Defect Diagnosis Based on Pattern-Dependent Stuck-at Faults / I. Pomeranz, S. Venkataraman, S. Reddy, E. Amyeen 475

Untestable Fault Identification Using Recurrence Relations and Impossible Value Assignments / M. Syal, M. Hsiao 481

Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults / H. Rahaman, D. Das, B. Bhattacharya 487

Open Defects Detection within 6T SRAM Cells Using a No Write Recovery Test Mode / J. Yang, B. Wang, A. Ivanov 493

Neural Network Model for Testing Stuck-at and Delay Faults in Digital Circuit / P. Zhongliang 499

Session 4D System on Chip

Challenges in the Design of Embedded Real-Time DSP SoCs / M. Mehendale 507

Multiprocessor Architectures for Embedded System-on-Chip Applications / C.P. Ravikumar 512

System-on-Chip (SoC): Clocking and Synchronization Issues / R. Sridhar 520

Package-Silicon Co-Design

Experiment with an SoC Design / P. Suresh, P. Sundararajan, A. Goel, H. Udayakumar, C. Srinivasan, V. Sinari, R. Ravinutala 531

Session 5A Analog Design

A Tunable g[subscript m]-C Filter with Low Variation across Process, Voltage and Temperature / Q. Khan, S. Wadhwa, K. Misri 539

The Influence of Process Variations on the Halo MOSFETs and Its Implications on the Analog Circuit Performance / K. Narasimhulu, S. Narendra, V. Rao 545

A CMOS Beta Multiplier Voltage Reference with Improved Temperature Performance and Silicon Tunability / S. Prasad, P. Mandal 551

Session 5B Design Methodology

Evaluation of Pausible Clocking for Interfacing High Speed IP Cores in GALS Framework / J. Mekie, S. Chakraborty, D. Sharma 559

A Novel Technique Towards Eliminating the Global Clock in VLSI Circuits / G. Hazari, M. Desai, A. Gupta, S. Chakraborty 565

A Distributed and Pipelined Controller for a Modular and Scalable Hardware Emulator / A. Mittal, M. Desai 571

Rapid Prototyping for Configurable System-on-a-Chip Platforms: A Simulation Based Approach / J. Bieger, S. Huss, M. Jung, S. Klaus, T. Steininger 577

Session 5C Test Pattern Generation

Can SAT Be Used to Improve Sequential ATPG Methods? / M. Prasad, M. Hsiao, J. Jain 585

Program Slicing for ATPG-Based Property Checking / V. Vedula, W. Townsend, J. Abraham 591

Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures / A. Kokrady, C.P. Ravikumar 597

Session 5D Embedded Systems

Embedded Systems / G. Berry

Tamper Resistance Mechanisms for Secure, Embedded Systems / S. Ravi, A. Raghunathan, S. Chakradhar 605

A Reduced Complexity 3rd Order Digital Delta-Sigma Modulator for Fractional-N Frequency Synthesis / R. Dehghani, S. Atarodi, B. Bornoosh, A. Kusha 615

A New Approach to Topology Selection for Cell-Level Analog Circuits / S. Nagar, B. Mazhari 619

Quantitative Model for Thermal Behaviour of an Analog Integrated Circuit / G. Sandha, P. Singh, C. Kumar, D. Nagchoudhuri 623

Chip Package Co-design of a Heterogeneously Integrated 2.45GHz CMOS VCO Using Embedded Passives in a Silicon Package / G. Nayak, P. Mukund 627

A Tuned Wideband LNA in 0.25[mu]m IBM Process for RF Communication Applications / M. Benmansour, P. Mukund 631

A Low Noise Current-Mode Readout Circuit for CMOS Image Sensing Applications / T. Das, P. Mukund 635

Sizing Consideration for Leakage Control Transistor / F. Farbiz, M. Farazian, M. Emadi, K. Sadeghi 639

A Quasi Static Model for a Simply Supported Beam in a Circuit Simulation Framework / S. Jairam, C. Venkatesh, N. Bhat, S. Singh, R. Pratap 642

Analytical Expressions for Static Characteristics of Submicron CMOS Inverters / S. Ulman 646

Real Time Dynamic Voltage Scaling for Embedded Systems / V. Rao, G. Singhal, A. Kumar 650

Designing Leakage Aware Multipliers / M. DeRenzo, M. Irwin, N. Vijaykrishnan 654

On Maximum Current Estimation in CMOS Digital Circuits / D. Ciuplys, P. Larsson-Edefors 658

Exploring the Novel Characteristics of Fully Depleted Dual-Material Gate (DMG) SOI MOSFET Using Two-Dimensional Numerical Simulation Studies / A. Chaudhry, M. Kumar 662

Analog VLSI Architecture for Discrete Cosine Transform Using Dynamic Switched Capacitors / A. Mal, A. Dhar 666

Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis / A. Murugavel, N. Ranganathan 670

An ASIC Implementation of Kohonen's Map Based Color Image Compression / N. Sudha 677

A Compact Low-Power Buffer Amplifier with Dynamic Bias Control Technique / C.-J. Yen, W.-Y. Chung, M. Chi 681

Preventing Crosstalk Delay Using Fibonacci Representation / M. Mutyam 685

An Area-Efficient Pipelined Array Architecture for Euclidean Distance Transformation and Its FPGA Implementation / N. Sudha 689

The Nostrum Backbone

A Communication Protocol Stack for Networks on Chip / M. Millberg, E. Nilsson, R. Thid, S. Kumar, A. Jantsch 693

VLSI Architecture of Centroid Tracking Algorithms for Video Tracker / M. Singh, B. Chauhan, N. Sharma 697

A Narrow Pulse-Suppressing Filter for Input Buffer / P. Mandal 701

Improved Approach for Noise Propagation to Identify Functional Noise Violations / S. Shrivastava, D. Varghese, V. Narang, N. Arvind 705

An Efficient Approach to Crosstalk Noise Analysis at Multiple Operating Modes / S. Chandrasekar, S. Shrivastava, A. Mandal, S. Ramanathan 709

Energy Model Based Macrocell Placement for Wirelength Minimization / S. Alupoaei, S. Katkoori 713

NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture / J. Chan, S. Parameswaran 717

Net Buffering in the Presence of Multiple Timing Views / R. Murgai 721

Path Based Approach for Crosstalk Delay Analysis / N. Arvind, K. Rajagopal, H. Ajith, S. Das 727

Carry Circuitry for LUT-Based FPGA / V. Jindal, A. Agarwal 731

An Optically Differential Reconfigurable Gate Array with a Partial Reconfiguration Optical System and Its Power Consumption Estimation / M. Watanabe, F. Kobayashi 735

On Interconnecting Circuits with Multiple Scan Chains for Improved Test Data Compression / I. Pomeranz, S. Reddy 741

ILP Models for Energy and Transient Power Minimization during Behavioral Synthesis / S. Mohanty, N. Ranganathan, S. Chappidi 745

Cycle-Accurate Energy Model and Source-Independent Characterization Methodology for Embedded Processors / S. Abrar 749

Built-in Self-Test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories / R. Sable, R. Saraf, R. Parekhji, A. Chandorkar 753

Synthesis of a Full Adder Circuit Using Reversible Logic / H. Babu, R. Islam, S. Chowdhury, A. Chowdhury 757

Performance Analysis of Inter-Cluster Communication Methods in VLIW Architecture / S. Saluja, A. Kumar 761

Boolean Decomposition Using Two-Literal Divisors / N. Modi, J. Cortadella 765

An Efficient Method to Generate Test Vectors for Combinational Cell Verification / N. Patel, M. Srihari, P. Maheswari, G. Nandakumar 769

Design of an Application Specific Instruction Set Processor for Parametric Speech Synthesis / R. Saini, P. Tanwar, A. Mandal, S. Bose, R. Singh, C. Shekhar 773

OaSis: An Application Specific Operating System for an Embedded Environment / G. Brar, S. Kundu, P. Worah, S. Biswas, A. Mukhopadhyay, A. Basu 776

Synthesis of Application Specific Multiprocessor Architectures for Process Networks / B. Dwivedi, A. Kumar, M. Balakrishnan 780

Enhancing SAT-Based Bounded Model Checking Using Sequential Logic Implications / R. Arora, M. Hsiao 784

Reset Careabouts in a SoC Design / S. Das, S. Chandar, A. Tiwari 788

VLSI Education: Should the Industry Decide the Curriculum?

Data-Driven Asynchronous Architecture and Its Implementation for Consumer Electronics / S. Miyata

Building Giga-Transistor [Enterprise] Microprocessors / R. Srinivas 801

Session 7A Device Physics

Device Reliability and Failure Mechanisms Related to Gate Dielectrics and Interconnects / M. Radhakrishnan 805

ESD Protection for the Deep Sub Micron Regime

A Challenge for Design Methodology / H. Gossner 809

Inclusion of Thermal Effects in the Simulation of Bipolar Circuits Using Circuit Level Behavioral Modeling / T. Shelar, G. Visweswaran 821

A New Surface Accumulation Layer Transistor(SALTran) Concept for Current Gain Enhancement in Bipolar Transistors / M. Kumar, V. Parihar 827

A Novel Technique for Steady State Analysis for VLSI Circuits in Partially Depleted SOI / R. Joshi, K. Kroell, C. Chuang 832

Session 7B Routing and Interconnect

High-Performance Power Grids for Nanometer Technologies / S. Sapatnekar 839

On-Chip Networks: A Scalable, Communication-Centric Embedded System Design Paradigm / J. Henkel, W. Wolf, S. Chakradhar 845

Shrubbery: A New Algorithm for Quickly Growing High-Quality Steiner Trees / G. Grewal, T. Wilson, M. Xu, D. Banerji 855

An Area Efficient Router for the Data-Intensive Architecture (DIVA) System / S. Mediratta, J. Sondeen, J. Draper 863

Estimating Pre-placement FPGA Interconnection Requirements / P. Kannan, D. Bhatia 869

Session 7C Testing

Digital Design: The Components of a New Paradigm / R. Gupta 877

Random Access Scan: A Solution to Test Power, Test Data Volume and Test Time / D. Baik, K. Saluja, S. Kajihara 883

Comparison of Effectiveness of Current Ratio and Delta-I[subscript DDQ] Tests / S. Sabade, D. Walker 889

At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories / X. Du, S. Reddy, W.-T. Cheng, J. Rayhawk, N. Mukherjee 895

Integrating Self Testability with Design Space Exploration by a Controller Based Estimation Technique / M. Gaur, M. Zwolinski 901

Evaluating the Reliability of Defect-Tolerant Architectures for Nanotechnology with Probabilistic Model Checking / G. Norman, D. Parker, M. Kwiatkowska, S. Shukla 907

Session 7D Processor Architecture

Application Specific Instruction Set Processors: Redefining Hardware-Software Boundary / C. Shekhar, R. Singh, A. Mandal, S. Bose, R. Saini, P. Tanwar 915

Synthesis-Driven Exploration of Pipelined Embedded Processors / P. Mishra, A. Kejariwal, N. Dutt 921

Cosynthesis of Multiprocessor Architectures with High Availability / S. Chakraverty 927

Instruction-Based Delay Fault Self-Testing of Processor Cores / V. Singh, M. Inoue, K. Saluja, H. Fujiwara 933

Session 8A UWB RF

Analog/RF Physical Layer Issues for UWB Systems / R. Harjani, J. Harvey, R. Sainati 941

UWB System Design / A. Tewfik

Katha-Mala: A Voice Output Communication Aid for the Children with Severe Speech and Multiple Disorders (SSMI) / A. Mukhopadhyay, P. Worah, S. Biswas, S. Biswas, R. Das, A. Basu 951

2nd Prize

High-Speed Optoelectronics Receivers in SiGe / A. Gupta, S. Levitan, L. Selavo, D. Chiarulli 957

Session 8B Layout and Placement

Ant Colony Optimization Technique for Macrocell Overlap Removal / S. Alupoaei, S. Katkoori 963

Constrained Floorplanning with Whitespace / Y. Feng, D. Mehta 969

Floorplan Classification Algorithms / K. Gao, D. Mehta 975

Maximum Multiplicity Distributions for Length Prediction Driven Placement / P. Anbalagan, J. Davis 981

Session 8C Noise Analysis

Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables / S. Batterywala, N. Shenoy 989

Application of Wavelets and Generalized Pencil-of-Function Method for the Extraction of Noise Current Spectrum and Simulation of Simultaneous Switching Noise / R. Mandrekar, M. Swaminathan, S. Chun 995

Dynamic Noise Margin: Definitions and Model / L. Ding, P. Mazumder 1001

Session 8D Analog and RF Test

Advanced LCD Timing Controller IC with Memory-Assisted Response Time Compensation / R. McCartney, N. Balram 1009

Concurrent RF Test Using Optimized Modulated RF Stimuli / S. Cherubal, R. Voorakaranam, A. Chatterjee, J. McLaughlin, J. Smith, D. Majernik 1017

A Current Sensor for On-Chip, Non-intrusive Testing of RF Systems / A. Soldo, A. Gopalan, P. Mukund, M. Margala 1023

A Built-in-Self-Test Scheme for Digital to Analog Converters / S. Rafeeque, V. Vasudevan 1027

Session 9A Low Power Design

CMOS Circuit Design for Minimum Dynamic Power and Highest Speed / T. Raja, V. Agrawal, M. Bushnell 1035

Dynamic Power Optimization for Interactive Systems / L. Zhong, N. Jha 1041

A Framework for Low Power Audio Design / N. Voss, B. Mertsching 1048

Session 9B H/W Impl. of Algorithms

An Efficient Algorithm to Construct Reduced Visibility Graph and Its FPGA Implementation / T. Priya, K. Sridharan 1057

VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design / S. Mohanty, N. Ranganathan, R. Namballa 1063

Session 9C Motion Estimation

A Parallel Architectural Implementation of the New Three-Step Search Algorithm for Block Motion Estimation / K. Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti, V. Kuteshwar 1071

An Architecture for Motion Estimation in the Transform Domain / J. Lee, N. Vijaykrishnan, M. Irwin, W. Wolf 1077

A 27 mW 1.1 mm[superscript 2] Motion Estimator for Picture-Rate Up-Converter / A. Beric, R. Sethuraman, H. Peters, J. van Meerbergen, G. de Haan, C. Pinto 1083

Call for Papers and Participation: The Eighteenth International Conference on VLSI Design 1089

Call for Papers and Participation: 8th IEEE VLSI Design & Test Workshops 1090.

Notes:

Includes bibliographical references and index.

ISBN:

0769520723

9780769520728

OCLC:

54395551

Access Restriction:

Restricted for use by site license.