18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. proceedings : 3-5 November, 2003, Boston, Massachusetts / sponsored by IEEE Computer Society Technology Technical Committee on Fault-Tolerant Computing (TCFTC) [and the] IEEE Computer Society Test Technology Technical Council (TTTC).

Format:

Book

Conference/Event

Contributor:

IEEE Xplore (Online service)

IEEE Computer Society. Fault-Tolerant Computing Technical Committee.

IEEE Computer Society. Test Technology Technical Committee.

Conference Name:

IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (18th : 2003 : Boston, Mass.)

Language:

English

Subjects (All):

Integrated circuits--Very large scale integration--Design and construction--Congresses.

Integrated circuits--Very large scale integration--Design and construction.

Fault-tolerant computing--Congresses.

Fault-tolerant computing.

Genre:

Conference papers and proceedings.

Physical Description:

xii, 607 pages : illustrations

Other Title:

International Symposium on Defect and Fault Tolerance in VLSI Systems

Defect and fault tolerance in VLSI systems

Halt t.p. title: DFT 2003

Place of Publication:

Los Alamitos, Calif. : IEEE Computer Society Press, [2003]

System Details:

Mode of access: World Wide Web.

text file

Contents:

Session 1 Yield and Defects

Yield Analysis of Compiler-Based Arrays of Embedded SRAMs / X. Wang, M. Ottavi, F. Lombardi 3

Reliability Estimation Model of IC's Interconnect Based on Uniform Distribution of Defects on a Chip / T. Zhao, X. Duan, Y. Hao 11

IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Wafer Scale Integration / M. Lu, Y. Savaria, B. Qiu, J. Taillefer 18

Calibration of Open Interconnect Yield Models / D. de Vries, P. Simon 26

Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults / T. Feng, N. Park, Y. Kim, V. Piuri 34

Session 2 Optoelectronics

Level-Hybrid Optoelectronic TESH Interconnection Network / V. Jain, G. Chapman 45

Implementation and Testing of Fault-Tolerant Photodiode-Based Active Pixel Sensor (APS) / S. Djaja, G. Chapman, D. Cheung, Y. Audet 53

Session 3 Fault Analysis, Injection & Simulation

Clock Calibration Faults and Their Impact on Quality of High Performance Microprocessors / C. Metra, T. Mak, D. Rossi 63

A Tool for Injecting SEU-Like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAs / M. Alderighi, F. Casini, S. D'Angelo, M. Mancini, A. Marmo, S. Pastore, G. Sechi 71

CodSim

A Combined Delay Fault Simulator / W. Qiu, X. Lu, Z. Li, D. Walker, W. Shi 79

Session 4 Test & Diagnosis

BIST Based Fault Diagnosis Using Ambiguous Test Set / H. Takahashi, Y. Tsugaoka, H. Ayano, Y. Takamatsu 89

On the Test and Diagnosis of the Perfect Shuffle / L. Schiano, F. Lombardi 97

Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption Standard / G. Bertoni, L. Breveglieri, I. Koren, P. Maistri, V. Piuri 105

Session 5 Current Test & Diagnosis

3DSDM: A 3 Data-Source Diagnostic Method / Y. Hariri, C. Thibeault 117

Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog Circuits / M. Dragic, M. Margala 124

CROWNE: Current Ratio Outliers with Neighbor Estimator / S. Sabade, D. Walker 132

Chip Level Power Supply Partitioning for I[subscript DDQ] Testing Using Built-In Current Sensors / A. Prasad, D. Walker 140

Session 6 Test Generation & Application

ATE-Amenable Test Data Compression with No Cyclic Scan Registers / H. Hashempour, F. Lombardi 151

A Digital and Wide Power Bandwidth H-Field Generator for Automatic Test Equipment / F. Zhang, Y. Lee, T. Kane, L. Schiano, M. Momenzadeh, Y.-B. Kim, F. Meyer, F. Lombardi, S. Max, P. Perkinson 159

Function-Based Dynamic Compaction and Its Impact on Test Set Sizes / J. Wingfield, J. Dworak, M. Mercer 167

Constrained ATPG for Broadside Transition Testing / X. Liu, M. Hsiao 175

Session 7 Scan Design & Test

Test Compaction by Using Linear-Matrix Driven Scan Chains / S. Bhatia 185

Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST / D. Ghosh, S. Bhunia, K. Roy 191

Design Scan Test Strategy for Single Phase Dynamic Circuits / C.-H. Cheng 199

Session 8 BIST

Scan-Based BIST Diagnosis Using an Embedded Processor / K. Balakrishnan, N. Touba 209

Hybrid BIST Using an Incrementally Guided LFSR / C. Krishna, N. Touba 217

Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture / G. Jervan, P. Eles, Z. Peng, R. Ubar, M. Jenihhin 225

Session 9 Error Correcting Codes

A Single Error Correcting and Double Error Detecting Coding Scheme for Computer Memory Systems / P. Lala 235

Array Codes Correcting a Cluster of Unidirectional Errors for Two-Dimensional Matrix Symbols / H. Kaneko, E. Fujiwara 242

Quadruple Time Redundancy Adders / W. Townsend, J. Abraham, E. Swartzlander, Jr. 250

Error Correcting Codes for Crosstalk Effect Minimization / D. Rossi, S. Cavallotti, C. Metra 257

Invited Talk

A View from the Bottom: Nanometer Technology AC Parametric Failures

Why, Where, and How to Detect / C. Hawkins, A. Keshavarzi, J. Segura 267

Session 10 Analogue & Mixed Signal Test

Analysis and Testing of Analog and Mixed-Signal Circuits by an Operation-Region Model: A Case Study of Application and Implementation / Y. Miura, D. Kato 279

An Approach for Selection of Test Points for Analog Fault Diagnosis / K. Pinjala, B. Kim 287

BiST Model for IC RF-Transceiver Front-End / J. Dabrowski 295

A Monolithic Spectral BIST Technique for Control or Test of Analog or Mixed-Signal Circuits / J. Emmert, J. Cheatham, B. Jagannathan, S. Umarani 303

Session 11 Defect Tolerance and Testing

Thermal Management of High Performance Microprocessors in Burn-In Environment / A. Vassighi, O. Semenov, M. Sachdev, A. Keshavarzi 313

Fault Recovery Based on Checkpointing for Hard Real-Time Embedded Systems / Y. Zhang, K. Chakrabarty 320

Fault Tolerant Multi-layer Neural Networks with GA Training / E. Sugawara, M. Fukushi, S. Horiguchi 328

Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels / A. Ammari, R. Leveugle, M. Sonza-Reorda, M. Violante 336

Low Cost Convolutional Code Based Concurrent Error Detection in FSMs / K. Rokas, Y. Makris, D. Gizopoulos 344

Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture / S. Sharifi, M. Hosseinabadi, P. Riahi, Z. Navabi 352

An FFT Approximation Technique Suitable for On-Chip Generation and Analysis of Sinusoidal Signals / J. Emmert, J. Cheatham, B. Jagannathan, S. Umarani 361

Fault Tolerant Hopfield Associative Memory on Torus / R. Ayoubi, H. Ziade, M. Bayoumi 369

Efficiency of Transient Bit-Flips Detection by Software Means: A Complete Study / B. Nicolescu, P. Peronnard, R. Velazco, Y. Savaria 377

Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip / A. Larsson, E. Larsson, P. Eles, Z. Peng 385

Regressive Testing for System-on-Chip with Unknown-Good-Yield / N.-J. Park, B. Jin, K. George, N. Park, M. Choi 393

Error Detection in Signed Digit Arithmetic Circuit with Parity Checker / G. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, A. Salsano 401

Application-Dependent Testing of FPGA Interconnects / M. Tahoori 409

Automatic Modification of Sequential Circuits for Self-Checking Implementation / C. Metra, S. Di Francescantonio, M. Omana 417

Control Constrained Resource Partitioning for Complex SoCs / D. Zhao, S. Upadhyaya, M. Margala 425

Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits / K. Mohanram, N. Touba 433

Session 12 FPGA & Memory Test

An Integrated Design Approach for Self-Checking FPGAs / C. Bolchini, F. Salice, D. Sciuto, R. Zavaglia 443

Power-Constrained Embedded Memory BIST Architecture / B. Fang, N. Nicolici 451

A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities / M. Nicolaidis, N. Achouri, L. Anghel 459

Redundancy, Repair, and Test Features of a 90nm Embedded SRAM Generator / R. Aitken, N. Dogra, D. Gandhi, S. Becker 467

An Efficient Functional Test for the Massively-Parallel C-RAM Logic-Enhanced Memory Architecture / X. Sun, B. Cockburn, D. Elliott 475

Session 13 Design Verification & Synthesis

Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models / H. Zarandi, S. Miremadi, A. Ejlali 485

Preliminary Validation of an Approach Dealing with Processor Obsolescence / L. Anghel, R. Velazco, S. Saleh, S. Deswaertes, A. El Moucary 493

Session 14 SoC & Core Test

Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA Core / G. Zeng, H. Ito 503

A Unified SoC Test Approach Based on Test Data Compression and TAM Design / V. Iyengar, A. Chandra 511

Embedded Compact Deterministic Test for IP-Protected Cores / A. Kinsman, J. Hewitt, N. Nicolici 519

Session 15 System Reliability

System-Level Analysis of Fault Effects in Automotive Environment / F. Corno, S. Tosato, P. Gabrielli 529

Dependability Analysis of CAN Networks: An Emulation-Based Approach / J. Perez, M. Sonza Reorda, M. Violante 537

Session 16 Fault Tolerance

Exploiting Instruction Redundancy for Transient Fault Tolerance / T. Sato 547

An Integrated Fault-Tolerant Design Framework for VLIW Processors / Y.-Y. Chen, S.-J. Horng, H.-C. Lai 555

Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code / S. Almukhaizim, Y. Makris 563

Heterogeneous Redundancy for Fault and Defect Tolerance with Complexity Independent Area Overhead / V. Kumar, J. Lach 571

Session 17 Soft Errors

Soft-Error Detection Using Control Flow Assertions / O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante 581

SIED: Software Implemented Error Detection / B. Nicolescu, Y. Savaria, R. Velazco 589

Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits / A. Maheshwari, I. Koren, W. Burleson 597.

Notes:

"IEEE Computer Society Order Number PR02042"--T.p. verso.

Includes bibliographical references and author index.

ISBN:

0769520421

9780769520421

OCLC:

53620221

Access Restriction:

Restricted for use by site license.