Euromicro Symposium on Digital System Design. [architectures, methods and tools] : proceedings : Belek-Antalya, Turkey, September 1st to 6th, 2003 / [Henry Selvaraj, program chair ; sponsored by Euromicro].

Format:

Book

Conference/Event

Contributor:

Selvaraj, Henry.

IEEE Xplore (Online service)

Euromicro.

Conference Name:

Euromicro Symposium on Digital Systems Design (2003 : Belek-Antalya, Turkey)

Language:

English

Subjects (All):

System design--Congresses.

System design.

Computer architecture--Congresses.

Computer architecture.

Digital electronics--Congresses.

Digital electronics.

Genre:

Conference papers and proceedings.

Physical Description:

xii, 478 pages : illustrations

Other Title:

Digital system design

DSD 2003

Place of Publication:

Los Alamitos, Calif. : IEEE Computer Society, [2003]

System Details:

Mode of access: World Wide Web.

text file

Contents:

Eccentric SoC Architectures as the Future Norm / G. Brebner 2

NoCs: A New Contract between Hardware and Software / A. Jantsch 10

Towards the Digitally Named World

Challenges for New Social Infrastructures Based on Information Technologies / H. Yasuura 17

Customizable Embedded Processor Architectures / P. Petrov, A. Orailoglu 468

Processor and Memory Architectures / Chair: W. Brunnbauer

Distance-aware L2 Cache Organizations for Scalable Multiprocessor Systems / S. Chung, H. Kim, C. Jhon 24

Unified Dual Data Caches / B. Juurlink 33

CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors / L. Li, N. Vijaykrishnan, M. Kandemir, M. Irwin, I. Kadayif 41

Synthesis (HL, LS, PS) / Chair: D. Dupont

Reversible Logic Synthesis for Minimization of Full-Adder Circuit / H. Babu, R. Islam, A. Chowdhury, S. Chowdhury 50

Scheduling and Assignment for Real-time Embedded Systems with Resource Contention / L. Pontani, D. Dupont 55

Multi Component Digital Circuit Optimization by Solving FSM Equations / N. Yevtushenko, S. Zharikova, M. Vetrova 62

Processor and Memory Architectures / Chair: B. Juurlink

DYNORA: A New Cache Technique / P. Srivatsan, P. Sudarshan, P. Bhaskaran 70

A Quadruple Precision and Dual Double Precision-Floating Point Multiplier / A. Akkas, M. Schulte 76

Causality Constraints for Processor Architectures with Sub-Word Parallelism / R. Schaffer, R. Merker, F. Catthoor 82

A Methodology for the Design of AHB Bus Master Wrappers / M. Bertola, G. Bois 90

Synthesis (HL, LS, PS) / Chair: J. Stine

A Constructive Algorithm with Look-Ahead for Mapping and Scheduling of Task Graphs with Conditional Edges / W. Brunnbauer, T. Wild, J. Foag, N. Pazos 98

An Application of Functional Decomposition in ROM-Based FSM Implementation in FPGA Devices / M. Rawski, H. Selvaraj, T. Luba 104

Processor and Memory Architectures / Chair: F. Leporati

Variations on Truncated Multiplication / J. Stine, O. Duverne 112

Exploring Storage Organization in ASIP Synthesis / M. Jain, M. Balakrishnan, A. Kumar 120

RDSP: A RISC DSP Based on Residue Number System / R. Chaves, L. Sousa 128

Synthesis (HL, LS, PS) / Chair: G. Kornaros

Operating Region Modelling of Deep-Submicron CMOS Buffers Driving Global Scope Inductive Interconnects / G. Cappuccino 138

A Scheduling and Partitioning Scheme for Low Power Circuit Operating at Multiple Voltages / L. Wang, H. Selvaraj 144

Information-driven Library-Based Circuit Synthesis / L. Jozwiak, S. Bieganski, A. Chojnacki 148

Special Architectures / Chair: L. Jozwiak 158

Low-power Branch Target Buffer for Application-Specific Embedded Processors / P. Petrov, A. Orailoglu 158

A Communication Model Based on an n-Dimensional Torus Architecture Using Deadlock-Free Wormhole Routing / P. Holzenspies, E. Schepers, W. Bach, M. Jonker, B. Sikkes, G. Smit, P. Havinga 166

A Development and Simulation Environment for a Floating Point Operations FPGA Based Accelerator / M. Bera, G. Danese, I. De Lotto, F. Leporati, A. Spelgatti 173

A Two-Step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture / T. Lei, S. Kumar 180

System-on-a-Chip / Chair: J. Stine

A Novel Specification Model for IP-Based Design / S. Klaus, S. Huss 190

An Efficient Implementation of Fair Load Balancing over Multi-CPU SOC Architectures / G. Kornaros, T. Orphanoudakis, N. Zervos 197

Special Architectures / Chair: M. Velev

Design and FPGA Implementation of a Video Scalar with On-chip Reduced Memory Utilization / S. Ramachandran, S. Srinivasan 206

Estimating the Utilization of Embedded FPGA Co-Processor / Y. Qu, J. Soininen 214

A Dynamically Reconfigurable Accelerator for Operations over Boolean and Ternary Vectors / V. Sklyarov, I. Skliarova, A. Oliveira, A. Ferrari 222

Fast Heuristics for the Edge Coloring of Large Graphs / M. Hilgemeier, N. Drechsler, R. Drechsler 230

Synthesis (HL, LS, PS) / Chair: H. Selvaraj

Back-End Dynamic Resource Allocation Heuristics for Power-Aware High-Performance Clustered Architectures / A. Baniasadi 240

NOAH, A Tool for Augument Reduction, Serial and Parallel Decomposition of Decision Tables / M. Pleban, H. Niewiadomski, P. Buciak, H. Selvaraj, P. Sapiecha, T. Luba 248

Design Tools and Resusable Libraries for FPGA-Based Digital Circuits / V. Sklyarov, I. Skliarova, P. Almeida, M. Almeida 255

HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming / K. Bhasyam, K. Bazargan 264

Reconfigurable Randomized K-way Graph Partitioning / F. Kocan 272

Multiple Voltage and Frequency Scheduling for Power Minimization / B. Radhakrishnan, M. Venkatesan 279

A Fast Additive Normalization Method for Exponential Computation / C. Chen, R. Chen, M. Sheu 286

A VLIW Architecture for Logarithmic Arithmetic / M. Arnold 294

System-on-a-Chip (2) and Validation/Verification / Chair: R. Ruzicka

Testable Design Verification Using Petri Nets / R. Ruzicka 304

Hierarchical Constraint Conscious RT-level Test Generation / O. Sinanoglu, A. Orailoglu 312

A System-on-Chip Implementation of the IEEE 802.11 a MAC Layer / G. Panic, D. Dietterle, Z. Stamenkovic, K. Tittelbach-Helmrich 319

The Application of Formal Verification to SPW Designs / B. Akbarpour, S. Tahar 325

Applications of (Embedded) Digital Systems / Chair: L. Lindh

Successful Prototyping of a Real-Time Hardware Based Terrain Navigation Correlator Algorithm / F. Traugott, K. Andersson, A. Lofgren, L. Lindh 334

A New Algorithm for High-Speed Projection in Point Rendering Applications / M. Amor, M. Boo, A. del Rio, M. Wand, W. Strasser 338

Sensor Platform Design for Automotive Applications / M. De Marinis, L. Fanucci, A. Giambastiani, A. Renieri, A. Rocchi, C. Rosadini, C. Sicilia, D. Sicilia 346

Specification and Modeling / Chair: A. Golda

Modelling and Simulation of a Digital IC System Using SimulPet: Application to a Speech Coding Communication IC / R. Fernandez-Ramos, J. Romero-Sanchez, F. Rios-Gomez, J. Martin-Canales 356

T&D-Bench+

A Software Environment for Modeling and Simulation of State-of-the-Art Processors / S. Soares, F. Wagner 362

Back-Traced Deductive-Parallel Fault Simulation for Digital Systems / V. Hahanov, R. Ubar, S. Hyduke 370

Temperature Influence on Power Consumption and Time Delay / A. Golda, A. Kos 378

Applications of (Embedded) Digital Systems / Chair: A. Lofgren

A Real Time Low Latency, FPGA Implementation of the 2-D Discrete Wavelet Transformation for Streaming Image Applications / O. Benderli, Y. Tekmen, N. Ismailoglu 384

Understanding Video Pixel Processing Applications for Flexible Implementations / O. Gangwal, J. Janssen, S. Rathnam, E. Bellers, M. Duranton 392

Power/Area Analysis and Optimization of a DS-SS Receiver for an Integrated Sensor Microsystem / N. Aydin, T. Arslan, D. Cumming 402

A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits / M. Muroyama, A. Hyodo, T. Okuma, H. Yasuura 408

Framed Complexity Analysis in SystemC for Multi-level Design Space Exploration / A. Wellig, J. Zory 416

Analytical Bounds on the Threads in IXP 1200 Network Processor / S. Ramakrishna, H. Jamadagni 426

Concurrent Operation Scheduling and Unit Allocation with an Evolutionary Technique / G. Papa, J. Silc 430

Exact Numerical Processing / J. Chamizo, J. Pascual, H. Mora 434

Stochastic Reconfigurable Hardware for Neural Networks / N. Nedjah, L. Mourelle 438

An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs / R. Czarnecki, S. Deniziak, K. Sapiecha 443

Distributing SoC Simulations over a Network of Computers / J. Riihimaki, V. Helminen, K. Kuusilinna, T. Hamalainen 447

FC-Min: A Fast Multi-Output Boolean Minimizer / P. Fiser, J. Hlavicka, H. Kubatova 451

A Methodology for Designing Communication Architectures for Multiprocessor SoCs / V. Dvorak, V. Kutalek 455

Compiler-Directed Management of Instruction Accesses / G. Chen, G. Chen, I. Kadayif, W. Zhang, M. Kandemir, I. Kolcu, U. Sezer 459

Test Scheduling for Embedded Systems / Z. Kotasek, D. Mika, J. Strnadel 463.

Notes:

"IEEE Computer Society Order Number PR02003"--T.p. verso.

Includes bibliographical references and author index.

ISBN:

0769520030

9780769520032

OCLC:

53028870

Access Restriction:

Restricted for use by site license.