Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing. (MTDT 2002) : 10-12 July, 2002, Isle of Bendor, France / editors, Bernard Courtois, Thomas Wik, Yervant Zorian ; sponsored by IEEE Computer Society, IEEE Computer Society Technical Council on Test Technology, IEEE Computer Society Technical Committee on VLSI ; in cooperation with IEEE Solid-State Circuits Society.

Format:

Book

Conference/Event

Contributor:

Courtois, B. (Bernard)

Wik, T. (Thomas)

Zorian, Yervant.

IEEE Xplore (Online service)

IEEE Computer Society.

IEEE Computer Society. Technical Committee on VLSI.

IEEE Computer Society. Technical Council on Test Technology.

IEEE Solid-State Circuits Society.

Conference Name:

IEEE International Workshop on Memory Technology, Design, and Testing (10th : 2002 : Isle of Bendor, France)

Language:

English

Subjects (All):

Semiconductor storage devices--Testing--Congresses.

Semiconductor storage devices.

Random access memory--Congresses.

Random access memory.

Semiconductor storage devices--Testing.

Genre:

Conference papers and proceedings.

Physical Description:

xii, 182 pages : illustrations

Other Title:

MTDT 2002

Memory technology, design and testing

Place of Publication:

Los Alamitos, Calif. : IEEE Computer Society, [2002]

System Details:

Mode of access: World Wide Web.

text file

Contents:

TTTC Information 180

Joint Session with The Eighth IEEE International On-Line Testing Workshop (IOLTW 2002)

Session A Plenary Session

Keynote Address: Embedded Memory Test and Repair / A. Kablanian

Session B Memory BIST Analysis and Application

Defect-Oriented Analysis of Memory BIST Tests / A. Jee 7

A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques / D. Appello, A. Fudoli, V. Tancorre, F. Corno, M. Rebaudengo, M. Sonza Reorda 12

A Scan-Bist Environment for Testing Embedded Memories / F. Karimi, F. Lombardi 17

Session C Memory ECC and Soft Errors

Soft Error Protection for Embedded Memories / M. Nicolaidis

Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories / D. Rossi, C. Metra, B. Ricco 27

High Speed 15 ns 4 Mbits SRAM for Space Application / B. Coloma, P. Delaunay, O. Husson 32

Session D High Reliability in Railway and Automotive Systems

The YATE Fail-Safe Interface: The User's Point of View / D. Bied-Charreton, D. Guillon, B. Jacques 39

Fault Tolerant Insertion and Verification: A Case Study / A. Manzone, D. De Costantini 44

Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems / L. Schiano, C. Metra, D. Marino 49

Session E Embedded Memory Yield Enhancement

A Silicon-Based Yield Gain Evaluation Methodology for Embedded-SRAMs with Different Redundancy Scenarios / E. Rondey, Y. Tellier, S. Borri 57

A March-Based Fault Location Algorithm for Static Random Access Memories / V. A. Vardanian, Y. Zorian 62

A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories / R.-F. Huang, J.-F. Li, J.-C. Yeh, C.-W. Wu 68

MTDT

Plenary Session

Keynote Address: Challenges and Opportunities Created by the SoC Shockwave / M. Templeton

Session 1 Embedded Memory Systems and Test Optimization

Design and Test of a 9-Port SRAM for a 100 Gb/s STS-1 Switch / R. Gibbins, R. D. Adams, T. Eckenrode, M. Ouellette, Y. Wu 83

Design of Embedded System for Video Coding with Logic-Enhanced DRAM and Configurable Process / T. Kaya, I. Shirakawa, R. Miyamoto, T. Onoye

Adder Merged DRAM Architecture / M. Hashimoto 88

Session 2 Memory Test Strategies

March SS: A Test for All Static Simple RAM Faults / S. Hamdioui, A. J. van de Goor, M. Rodgers 95

Random Testing of Multi-Port Static Random Access Memories / F. Karimi, F. J. Meyer, F. Lombardi 101

Session 3 Fault Modeling

A Fault Modeling Technique to Test Memory BIST Algorithms / R. Venkatesh, S. Kumar, J. Philip, S. Shukla 109

Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM / M. Redeker, B. F. Cockburn, D. G. Elliott, Y. Xiang, S. A. Ung 117

An Investigation into Crosstalk Noise in DRAM Structures / M. Redeker, B. F. Cockburn, D. G. Elliott 123

Session 4 Embedded Memory Compiler Tutorial

Keynote Address: SoC's Trends and Challenges going to 0.10 [mu]m / P. Magarshack

Session 5 EPROM/EEPROM Design

An Automated Design Methodology for EEPROM Cell (ADE) / J. M. Portal, L. Forli, H. Aziza, D. Nee 137

A Novel Memory Array Based on an Annular Single-Poly EPROM Cell for Use in Standard CMOS Technology / C. Dray, P. Gendrier 143

A New Single Ended Sense Amplifier for Low Voltage Embedded EEPROM Non Volatile Memories / C. Papaix, J. M. Daga 149

Session 6 Process Technology and Reliability

Validated 90 nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC) / T. Devoivre, M. Lunenborg, C. Julien, J-P. Carrere, P. Ferreira, W. J. Toren, A. VandeGoor, P. Gayet, T. Berger, O. Hinsinger, P. Vannier, Y. Trouiller, Y. Rody, P-J. Goirand, R. Palla, I. Thomas, F. Guyader, D. Roy, B. Borot, N. Planes, S. Naudet, F. Pico, D. Duca, F. Lalanne, D. Heslinga, M. Haond 157

Converting an Embedded Low-Power SRAM from Bulk to PD-SOI / M. R. Casu, P. Flatresse 163

Decreasing EEPROM Programming Bias with Negative Voltage, Reliability Impact / R. Laffont, J. Razafindramora, P. Canet, R. Bouchakour, J. M. Mirabel 168

Session 7 Advanced Memory Technologies Panel

Panel on Advanced Embedded Memory Technologies / B. F. Cockburn 177.

Notes:

"IEEE Computer Society Order Number PR01617"--T.p. verso.

" ... 10th anniversary of the Workshop ..."--P. x.

Includes bibliographical references and index.

ISBN:

0769516173

9780769516172

0769516181

9780769516189

076951619X

9780769516196

OCLC:

50761453

Access Restriction:

Restricted for use by site license.