21st International Conference on Computer Design. proceedings : October 13 to 15, 2003, San Jose, California / sponsored by IEEE Computer Society, IEEE Circuits and Systems Society ; in cooperation with IEEE Electron Devices Society.

Format:

Book

Conference/Event

Contributor:

IEEE Xplore (Online service)

IEEE Computer Society.

IEEE Circuits and Systems Society.

IEEE Electron Devices Society.

Conference Name:

IEEE International Conference on Computer Design (21st : 2003 : San Jose, Calif.)

Language:

English

Subjects (All):

Microcomputers--Design and construction--Congresses.

Microcomputers.

Electronic digital computers--Circuits--Congresses.

Electronic digital computers.

Electronic digital computers--Circuits.

Integrated circuits--Very large scale integration--Congresses.

Integrated circuits.

Integrated circuits--Very large scale integration.

Computer engineering--Congresses.

Computer engineering.

Microcomputers--Design and construction.

Genre:

Conference papers and proceedings.

Physical Description:

xxii, 563 pages : illustrations

Other Title:

International Conference on Computer Design

ICCD 2003

Computer design, 2003, proceedings, 21st International Conference on.

Place of Publication:

Los Alamitos, Calif. : IEEE Computer Society, [2003]

System Details:

Mode of access: World Wide Web.

text file

Contents:

High-Speed Link Design, Then and Now / M. Horowitz xx

Terascale Computing and BlueGene / W. Pulleyblank xxi

Advanced EDA Tools for High-Performance Design / T. Vucurevich xxii

Session 1.1 Energy Efficiency

Energy Efficient Asymmetrically Ported Register Files / A. Aggarwal, M. Franklin 2

Power Efficient Data Cache Designs / J. Abella, A. Gonzalez 8

On Reducing Register Pressure and Energy in Multiple-Banked Register Files / J. Abella, A. Gonzalez 14

Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition / M. Ito, D. Chinnery, K. Keutzer 21

Session 1.2 Timing Verification

Verification of Timed Circuits with Failure Directed Abstractions / H. Zheng, C. Myers, D. Walter, S. Little, T. Yoneda 28

Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits / G. Chen, S. Reddy, I. Pomeranz 36

Event-Centric Simulation of Crosstalk Pulse Faults in Sequential Circuits / M. Phadoongsidhi, K. Saluja 42

Specifying and Verifying Systems with Multiple Clocks / E. Clarke, D. Kroening, K. Yorav 48

Session 1.3 Electrical Analysis for System LSI

Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics / W. Yu, Z. Wang, X. Hong 58

An Improved Method for Fast Noise Estimation Based on Net Segmentation / C. Huang, A. Dasgupta 64

Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current / H. Song, S. Bohidar, I. Bahar, J. Grodstein 70

An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk / V. Rajappan, S. Sapatnekar 76

Session 2.1 Power Optimization

A Compact Model for Analysis and Design of On-chip Power Network with Decoupling Capacitors / P. Zarkesh-Ha, K. Doniger, W. Loh, D. Sun, R. Stephani, G. Priebe 84

Precomputation-Based Guarding for Dynamic and Leakage Power Reduction / A. Abddollahi, M. Pedram, F. Fallah, I. Ghosh 90

Charge-Recycling Voltage Domains for Energy-Efficient Low-Voltage Operation of Digital CMOS Circuits / S. Rajapandian, Z. Xu, K. Shepard 98

Low Power Adder with Adaptive Supply Voltage / H. Suzuki, W. Jeong, K. Roy 103

A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File / N. Tzartzanis, W. Walker 107

Session 2.2 Invited Session: Gene Chip Design

Detection of Biological Molecules: From Self-Assembled Films to Self-Integrated Devices / R. Levicky 112

Embedded Tutorial

Design Flow Enhancements for DNA Arrays / A. Kahng, I. Mandoiu, S. Reda, X. Xu, A. Zelikovsky 116

Session 2.3 System Level Design

Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip / N. Thepayasuwan, V. Damle, A. Doboli 126

Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs / V. Chandra, G. Carpenter, J. Burns 134

Interface Synthesis Using Memory Mapping for an FPGA Platform / M. Luthra, S. Gupta, N. Dutt, R. Gupta, A. Nicolau 140

Efficient Synthesis of Networks On Chip / A. Pinto, L. Carloni, A. Sangiovanni-Vincentelli 146

Reducing Compilation Time Overhead in Compiled Simulators / M. Reshadi, N. Dutt 151

Session 3.1 Systems Performance

Profiling Interrupt Handler Performance through Kernel Instrumentation / B. Moore, T. Slabach, L. Schaelicke 156

Design and Performance of Compressed Interconnects for High Performance Servers / K. Kant, R. Iyer 164

Routed Inter-ALU Networks for ILP Scalability and Performance / K. Sankaralingam, V. Singh, S. Keckler, D. Burger 170

Session 3.2 Micro Processor Test & Diagnosis

Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor / J. Grodstein, D. Bhavsar, V. Bettada, R. Davies 180

Test Generation for Non-separable RTL Controller-datapath Circuits Using a Satisfiability Based Approach / L. Lingappan, S. Ravi, N. Jha 187

Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case / S. Almukhaizim, T. Verdel, Y. Makris 194

Multiple Fault Diagnosis Using n-Detection Tests / Z. Wang, M. Marek-Sadowska, K. Tsai, J. Rajski 198

Session 3.3 Physical Design

A Physical Design Methodology for 1.3GHz SPARC64 Microprocessor / N. Ito, H. Komatsu, Y. Tanamura, R. Yamashita, H. Sugiyama, Y. Sugiyama, H. Hamamura 204

Physical Design of the "2.5D" Stacked System / Y. Deng, W. Maly 211

Flow-Based Cell Moving Algorithm for Desired Cell Distribution / B. Choi, H. Xu, M. Wang, M. Sarrafzadeh 218

Session 4.1 Performance Optimization

NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors / B. Lee, L. John 226

Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis / N. Mahapatra, J. Liu, K. Sundaresan 234

Pipelined Multiplicative Division with IEEE Rounding / G. Even, P. Seidel 240

Session 4.2 Clock & Signal Distribution

Design of Resonant Global Clock Distributions / S. Chan, K. Shepard, P. Restley 248

Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links / G. Balamurugan, N. Shanbhag 254

A Mixed-Mode Delay-Locked Loop Architecture / D. Eckerbert, L. Svensson, P. Larsson-Edefors 261

Optimal Inductance for On-chip RLC Interconnections / S. Das, K. Agarwal, D. Blaauw, D. Sylvester 264

Session 4.3 Performance and Power-Driven Physical Design

Spec Based Flip-Flop and Buffer Insertion / N. Akkiraju, M. Mohan 270

A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization / N. Ranganathan, A. Murugavel 276

A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing / R. Chaturvedi, J. Hu 282

Session 5.1 Instruction Execution

Hardware-Based Pointer Data Prefetcher / S. Lai, S. Lu 290

A Dependence Driven Efficient Dispatch Scheme / S. Nadathur, A. Tyagi 299

An Efficient VLIW DSP Architecture for Baseband Processing / T. Lin, C. Chang, C. Lee, C. Jen 307

Dynamic Thread Resizing for Speculative Multithreaded Processors / M. Zahran, M. Franklin 313

Session 5.2 Invited Session: Test Compression Technology

Care Bit Density and Test Cube Clusters: Multi-Level Compression Opportunities / B. Koenemann 320

XMAX: X-Tolerant Architecture for MAXimal Test Compression / S. Mitra, K. Kim 326

Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs / J. Rajski, J. Tyszer 331

Session 5.3 Physical Design for Regular Fabrics and FPGA's

Non-Crossing OBDDs for Mapping to Regular Circuit Structures / A. Cao, C. Koh 338

Interconnect Estimation for FPGAs under Timing Driven Domains / P. Kannan, D. Bhatia 344

ROAD: An Order-Impervious Optimal Detailed Router for FPGAs / H. Arslan, S. Dutt 350

Session 6.1 Array Design Optimization

Reducing dTLB Energy through Dynamic Resizing / V. Delaluz, M. Kandemir, A. Sivasubramaniam, M. Irwin, N. Vijaykrishnan 358

Distributed Reorder Buffer Schemes for Low Power / G. Kucuk, O. Ergin, D. Ponomarev, K. Ghose 364

Virtual Page Tag Reduction for Low-Power TLBs / P. Petrov, A. Orailoglu 371

Dynamic Cluster Resizing / J. Gonzalez, A. Gonzalez 375

Session 6.2 Test Compaction

Independent Test Sequence Compaction through Integer Programming / P. Drineas, Y. Makris 380

On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume / S. Kajihara, Y. Doi, L. Li, K. Chakrabarty 387

Static Test Compaction for Multiple Full-Scan Circuits / I. Pomeranz, S. Reddy 393

A Method to Find Don't Care Values in Test Sequences for Sequential Circuits / Y. Higami, S. Kobayashi, Y. Takamatsu, S. Kajihara, I. Pomeranz 397

Session 6.3 Invited Session: Techniques for Synthesizing into Fabrics

Simplifying SoC Design with the Customizable Control Processor Platform / C. Ogilvie, R. Ray, R. Devins, M. Kautzman, M. Hale, R. Bergamaschi, B. Lynch, S. Gaur 402

Structured ASICs: Opportunities and Challenges / B. Zahiri 404

System LSI Implementation Fabrics for the Future / S. Kaptanoglu 410

Session 7.1 Hardware Partitioning

Multiple-V[subscript dd] Scheduling/Allocation for Partitioned Floorplan / D. Kang, M. Johnson, K. Roy 412

SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs Using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture / Y. Kwon, B. Park, C. Kyung 419

A Study of Hardware Techniques that Dynamically Exploit Frequent Operands to Reduce Power Consumption in Integer Function Units / K. Gandhi, N. Mahapatra 426

Session 7.2 Energy-Aware Design and Application

KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths / C. Gopalakrishnan, S. Katkoori 430

A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits / M. Mukherjee, R. Vemuri 436

Power Fluctuation Minimization During Behavioral Synthesis Using ILP-Based Datapath Scheduling / S. Mohanty, N. Ranganathan, S. Chappidi 441

An Energy-Aware Simulation Model and Transaction Protocol for Dynamic Workload Distribution in Mobile Ad Hoc Networks / F. Ghasemi-Tari, P. Rong, M. Pedram 444

Session 7.3 Invited Session: High-Speed Design Issues and Test Challenges

CMOS High-Speed Serial I/Os

Present and Future / M. Lee, W. Dally, R. Farjad-Rad, H. Ng, R. Senthinathan, J. Edmondson, J. Poulton 454

Fully Differential Receiver Chipset for 40 Gb/s Applications Using GaInAs/InP Single Heterojunction Bipolar Transistors / K. Kiziloglu, S. Seetharaman, K. Glass, C. Bil, H. Duong, G. Asmanis 462

Paradigm Shift for Jitter and Noise in Design and Test [greater than sign]GB/s Data Communication Systems / M. Li, J. Wilstrup 467

Session 8.1 Efficiency and Reliability

Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems / C. Park, J. Seo, D. Seo, S. Kim, B. Kim 474

Exploiting Microarchitectural Redundancy for Defect Tolerance / P. Shivakumar, S. Keckler, C. Moore, D. Burger 481

Reducing Multimedia Decode Power Using Feedback Control / Z. Lu, J. Lach, M. Stan, K. Skadron 489

Session 8.2 Novel Methods in Logic Synthesis

Structural Detection of Symmetries in Boolean Functions / G. Wang, A. Kuehlmann, A. Sangiovanni-Vincentelli 498

Boolean Decomposition Based on Cyclic Chains / E. Dubrova, M. Teslenko, J. Karlsson 504

SAT-Based Algorithms for Logic Minimization / S. Sapra, M. Theobald, E. Clarke 510

Session 9.1 Communications and Context Management

Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels / A. Selvarathinam, E. Kim, G. Choi 520

Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Coniext Switches / S. Pasricha, A. Veidenbaum 526

Reducing Operand Transport Complexity of Superscalar Processors Using Distributed Register Files / S. Bunchua, D. Wills, L. Wills 532

xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture for Multi-Processor SoCs / M. Dall'Osso, G. Biccari, L. Giovannini, D. Bertozzi, L. Benini 536

Session 9.2 Board Test and Power-Aware Test

Aggressive Test Power Reduction through Test Stimuli Transformation / O. Sinanoglu, A. Orailoglu 542

Power-Time Tradeoff in Test Scheduling for SoCs / M. Nourani, J. Chin 548

Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity / M. Tehranipour, N. Ahmed, M. Nourani 554.

Notes:

"IEEE Computer Society Order Number PR02025"--T.p. verso.

"ICCD 2003"--Cover.

Includes bibliographical references and author index.

ISBN:

0769520251

9780769520254

OCLC:

53335768

Access Restriction:

Restricted for use by site license.