IEEE International Conference on Application-Specific Systems, Architectures and Processors. proceedings : ASAP 2003 : 24-26 June, 2003, the Hague, the Netherlands / edited by Ed Deprettere ... [and others] ; sponsored by IEEE Computer Society.

Format:

Book

Conference/Event

Contributor:

Deprettere, Ed. F., 1944-

IEEE Xplore (Online service)

IEEE Computer Society.

Conference Name:

International Conference on Application-Specific Systems, Architectures, and Processors (14th : 2003 : The Hague, The Netherlands)

Language:

English

Subjects (All):

Array processors--Congresses.

Array processors.

Signal processing--Digital techniques--Congresses.

Signal processing.

Signal processing--Digital techniques.

Application-specific integrated circuits--Congresses.

Application-specific integrated circuits.

Genre:

Conference papers and proceedings.

Physical Description:

x, 470 pages : illustrations

Other Title:

Application specific systems, architectures, and processors

ASAP 2003

Application-Specific Systems, Architectures, and Processors, 2003, proceedings, IEEE International Conference on.

Place of Publication:

Los Alamitos, Calif. : IEEE Computer Society, [2003]

System Details:

Mode of access: World Wide Web.

text file

Contents:

Challenges in the Design of Security-Aware Processors / R. Lee 2

Session 1 Models, Methods and Tools

Context-Aware Process Networks / H. van Dijk, H. Sips, E. Deprettere 6

Multi-Dimensional Incremental Loop Fusion for Data Locality / S. Verdoolaege, M. Bruynooghe, G. Janssens, F. Catthoor 17

Switched Memory Architectures

Moving Beyond Systolic Arrays / R. Lakshminarayanan, S. Rajopadhye 28

Hardware Synthesis for Multi-Dimensional Time / A.-C. Guillou, P. Quinton, T. Risset 40

Using Group Theory to Specify Application Specific Interconnection Networks for SIMD DSPs / T. Drager, G. Fettweis 51

Session 2 Design Methodology

Systematic Register Bypass Customization for Application-Specific Processors / K. Fan, N. Clark, M. Chu, K. Manjunath, R. Ravindran, M. Smelyanskiy, S. Mahlke 64

Storage Management in Process Networks Using the Lexicographically Maximal Preimage / A. Turjan, B. Kienhuis 75

Energy Aware Register File Implementation through Instruction Predecode / J. Ayala, M. Lopez-Vallejo, A. Veidenbaum, C. Lopez 86

Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics / T. Ye, G. De Micheli 97

Automatic Instruction Set Extension and Utilization for Embedded Processors / A. Peymandoust, L. Pozzi, P. Ienne, G. De Micheli 108

Session 3 Invited Session

Nanocomputing Technology and Systems

Nanotechnology in the Development of Future Computing Systems / T. Yamada, M. Meyyappan 120

Circuit Characteristics of Molecular Electronic Components / D. Janes, S. Ghosh, J. Choi, S. Lodha, S. Bhattacharya 125

Reconfigurable Computing and Electronic Nanotechnology / S. Goldstein, M. Budiu, M. Mishra, G. Venkataramani 132

Session 4 Processors

Using Media Processors for Low-Memory AES Implementation / J. Irwin, D. Page 144

Variable-Length Instruction Compression for Area Minimization / P. Simonen, I. Saastamoinen, J. Nurmi 155

A Generic Tool-Set for SoC Multiprocessor Debugging and Synchronization / A. Wieferink, T. Kogel, R. Leupers, H. Meyr, A. Nohl, A. Hoffmann 161

Evaluating Memory Architectures for Media Applications on Coarse-Grained Reconfigurable Architectures / J.-e. Lee, K. Choi, N. Dutt 172

Application-Specific Computing with Adaptive Register File Architectures / R. Sangireddy, A. Somani 183

Session 5 Numeric Co-Processors

A Floating-Point CORDIC Based SVD Processor / Z. Liu, K. Dickson, J. McCanny 194

Combined Multiplication and Sum-of-Squares Units / M. Schulte, L. Marquette, S. Krithivasan, E. Walters III, J. Glossner 204

Comparison of Branching CORDIC Implementations / A. Singh, D. Phatak, T. Goff, M. Riggs, J. Plusquellic, C. Patel 215

Unified Radix-4 Multiplier for GF(p) and GF(2[superscript n]) / L.-S. Au, N. Burgess 226

Arbitrary Bit Permutations in One or Two Cycles / Z. Shi, X. Yang, R. Lee 237

Session 6 Multimedia Architectures

Color Space Conversion for MPEG Decoding on FPGA-Augmented TriMedia Processor / M. Sima, S. Vassiliadis, S. Cotofana, J. van Eijndhoven 250

Reducing Dynamic Power Consumption in Next Generation DS-CDMA Mobile Communication Receivers / V. Chandrasekhar, F. Livingston, J. Cavallaro 260

An Efficient Disk-Array-Based Server Design for a Multicast Video Streaming System / P. Chan, J. Lee 271

An Efficient PIM (Processor-In-Memory) Architecture for Motion Estimation / J.-Y. Kang, S. Gupta, S. Shah, J.-L. Gaudiot 282

A VLSI Architecture for Advanced Video Coding Motion Estimation / S. Yap, J. McCanny 293

Session 7 Computer Arithmetic

Complex Division with Prescaling of Operands / M. Ercegovac, J.-M. Muller 304

Iterative Methods for Logarithmic Subtraction / M. Arnold 315

A Family of Parallel-Prefix Modulo 2[superscript n] - 1 Adders / G. Dimitrakopoulos, H. Vergos, D. Nikolos, C. Efstathiou 326

Performance-Improved Computation of Very Large Word-Length LNS Addition/Subtraction Using Signed-Digit Arithmetic / C. Chen, R.-L. Chen 337

Decimal Multiplication Via Carry-Save Addition / M. Erle, M. Schulte 348

Session 8 Signal Processing Architectures

Reconfigurable Viterbi Decoding Using a New ACS Pipelining Technique / Y. Zhu, M. Benaissa 360

Application-Specific DSP Architecture for Fast Fourier Transform / K. Heo, S. Cho, J. Lee, M. Sunwoo 369

An Architecture for a Radix-4 Modular Pipeline Fast Fourier Transform / A. El-Khashab, E. Swartzlander, Jr 378

GFS: An Efficient Implementation of Fair Scheduling for Multi-Gigabit Packet Networks / G. Kornaros, T. Orphanoudakis, I. Papaefstathiou 389

Area and Time Efficient Modular Multiplication of Large Integers / V. Bunimov, M. Schimmler 400

Session 9 Cryptography

Modular Multiplication for FPGA Implementation of the IDEA Block Cipher / J.-L. Beuchat 412

Concurrent Fault Detection in a Hardware Implementation of the RC5 Encryption Algorithm / G. Bertoni, L. Breveglieri, I. Koren, P. Maistri, V. Piuri 423

Hardware Implementation of an Elliptic Curve Processor over GF(p) / S. Ors, L. Batina, B. Preneel, J. Vandewalle 433

A Cryptographic Processor for Arbitrary Elliptic Curves over GF(2[superscript m]) / H. Eberle, N. Gura, S. Chang-Shantz 444

Instruction Set Extension for Fast Elliptic Curve Cryptography over Binary Finite Fields GF(2[superscript m]) / J. Grossschadl, G.-A. Kamendje 455.

Notes:

"IEEE Computer Society Order Number PR01992"--T.p. verso.

Includes bibliographical references and author index.

ISBN:

076951992X

9780769519920

OCLC:

52624868

Access Restriction:

Restricted for use by site license.