11th Asian Test Symposium (ATS'02). proceedings of the 11th Asian Test Symposium : 18-20 November, 2002, Guam, USA / sponsored by the IEEE Computer Society Test Technology Technical Council (TTTC) ; in cooperation with Technical Group on Dependable Computing, IEICE, Special Interest Group on System LSI Design Methodology, IPS Japan.

Format:

Book

Conference/Event

Contributor:

IEEE Xplore (Online service)

IEEE Computer Society. Test Technology Technical Committee.

Denshi Jōhō Tsūshin Gakkai (Japan). Technical Group on Dependable Computing.

Special Interest Group on System LSI Design Methodology (Japan)

Conference Name:

Asian Test Symposium (11th : 2002 : Guam)

Language:

English

Subjects (All):

Electronic digital computers--Circuits--Testing--Congresses.

Electronic digital computers--Circuits--Testing.

Electronic circuits--Testing--Congresses.

Fault-tolerant computing--Congresses.

Fault-tolerant computing.

Electronic circuits--Testing.

Genre:

Conference papers and proceedings.

Physical Description:

xxi, 437 pages : illustrations

Other Title:

ATS'02

Test Symposium, 2002, (ATS '02), proceedings of the 11th Asian.

Place of Publication:

Los Alamitos, Calif. : IEEE Computer Society, [2002]

System Details:

Mode of access: World Wide Web.

text file

Contents:

Session 1A Test Generation

On Generating High Quality Tests for Transition Faults / Y. Shao, I. Pomeranz, S. Reddy 1

Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests / I. Polian, I. Pomeranz, B. Becker 9

Maximum Distance Testing / S. Xu, J. Chen 15

Session 1B On-Line Testing

High Precision Result Evaluation of VLSI / J. Hirase 21

A Totally Self-Checking Dynamic Asynchronous Datapath / J.-L. Yang, C.-S. Choy, C.-F. Chan, K.-P. Pun 27

Non-intrusive Design of Concurrently Self-Testable FSMs / P. Drineas, Y. Makris 33

Session 1C Analog and Mixed Signal Testing

Test Limitations of Parametric Faults in Analog Circuits / J. Savir, Z. Guo 39

Effects of Amplitude Modulation in Jitter Tolerance Measurements of Communication Devices / M. Ishida, T. Yamaguchi, M. Soma, H. Musha 45

On-Chip Analog Response Extraction with 1-Bit [Sigma]-[delta] Modulators / H.-C. Hong, J.-L. Huang, K.-T. Cheng, C.-W. Wu 49

Session 2A Test Set Compaction

A State Reduction Method for Non-scan Based FSM Testing with Don't Care Inputs Identification Technique / T. Hosokawa, H. Date, M. Muraoka 55

Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test Sequences / I. Pomeranz, S. Reddy 61

Test Data Compression Using Don't-Care Identification and Statistical Encoding / S. Kajihara, K. Taniguchi, K. Miyase, I. Pomeranz, S. Reddy 67

Session 2B Design for Testability

Design for Two-Pattern Testability of Controller-Data Path Circuits / Md. Altaf-Ul-Amin, S. Ohtake, H. Fujiwara 73

MD-SCAN Method for Low Power Scan Testing / T. Yoshida, M. Watari 80

Non-scan Design for Testability Based on Fault Oriented Conflict Analysis / D. Xiang, S. Gu, H. Fujiwara 86

Session 2C Memory Testing 1

Specification and Design of a New Memory Fault Simulator / A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto 92

DRAM Specific Approximation of the Faulty Behavior of Cell Defects / Z. Al-Ars, Ad J. van de Goor 98

An Access Timing Measurement Unit of Embedded Memory / S.-R. Lee, M.-J. Hsiao, T.-Y. Chang 104

Session 3A Delay Fault Testing

A Partitioning and Storage Based Built-in Test Pattern Generation Method for Delay Faults in Scan Circuits / I. Pomeranz, S. Reddy 110

Optimal Seed Generation for Delay Fault Detection BIST / L. Tong, K. Suzuki, H. Ito 116

On-Chip Tap-Delay Measurements for a Digital Delay-Line Used in High-Speed Inter-Chip Data Communications / O. Petre, H. Kerkhoff 122

Session 3B Test Synthesis

A Scheduling Method in High-Level Synthesis for Acyclic Partial Scan Design / T. Inoue, T. Miura, A. Tamura, H. Fujiwara 128

Test Requirement Analysis for Low Cost Hierarchical Test Path Construction / Y. Makris, A. Orailoglu 134

Testable Realizations for ESOP Expressions of Logic Functions / P. Zhongliang 140

Session 3C Memory Testing 2

DPSC SRAM Transparent Test Algorithm / H.-S. Kim, S. Kang 145

Tests for Word-Oriented Content Addressable Memories / Z. Xuemei, Y. Yizheng, C. Chunxu 151

A High Performance I[subscript DDQ] Testable Cache for Scaled CMOS Technologies / S. Bhunia, H. Li, K. Roy 157

Session 4A Crosstalk Fault Testing

Enhanced Crosstalk Fault Model and Methodology to Generate Tests for Arbitrary Inter-core Interconnect Topology / W. Sirisaengtaksin, S. Gupta 163

A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal / M. Wu, C. Lee, C. Chang, J. Chen 170

Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits / K. Shimizu, N. Itazaki, K. Kinoshita 176

A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits / M. Phadoongsidhi, K. Le, K. Saluja 182

Session 4B Built-in Self Test 1

Efficient Circuit Specific Pseudoexhaustive Testing with Cellular Automata / S. Chattopadhyay 188

Fault Set Partition for Efficient Width Compression / E. Gizdarski, H. Fujiwara 194

A Reseeding Technique for LFSR-Based BIST Applications / N.-C. Lai, S.-J. Wang 200

A ROMless LFSR Reseeding Scheme for Scan-Based BIST / E. Kalligeros, X. Kavousianos, D. Nikolos 206

Session 4C Fault-Tolerance

A Fault-Tolerant Architecture for Symmetric Block Ciphers / M.-K. Joo, J.-H. Kim, Y.-H. Choi 212

A New Learning Approach to Design Fault Tolerant ANNs: Finally a Zero HW-SW Overhead / F. Vargas, D. Lettnin, D. Brum, D. Prestes 218

Experimental Results of a Recovery Block Scheme to Handle Noise in Speech Recognition Systems / F. Vargas, R. Fagundes, D. Barros, Jr. 224

Easily Testable and Fault-Tolerant Design of FFT Butterfly Networks / S.-K. Lu, C.-H. Yeh 230

Session 5A Fault Detection and Diagnosis

Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGA's / S.-K. Lu, C.-Y. Chen 236

Reduction of Target Fault List for Crosstalk-Induced Delay Faults by Using Layout Constraints / K. Keller, H. Takahashi, K. Le, K. Saluja, Y. Takamatsu 242

Diagnosis of Byzantine Open-Segment Faults / S.-Y. Huang 248

Session 5B Built-in Self Test 2

Robust Space Compaction of Test Responses / A. Dmitriev, M. Gossel, K. Chakrabarty 254

An Evolutionary Strategy to Design an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS) / N. Ganguly, A. Nandi, S. Das, B. Sikdar, P. Chaudhuri 260

An Embedded Built-in-Self-Test Approach for Analog-to-Digital Converters / S.-H. Hsieh, M.-J. Hsiao, T.-Y. Chang 266

Session 5C Software Testing

Statistical Analysis of Time Series Data on the Number of Faults Detected by Software Testing / S. Amasaki, T. Yoshitomi, O. Mizuno, T. Kikuno, Y. Takagi 272

An Analytic Software Testability Model / J.-C. Lin, S.-W. Lin 278

Effective Automated Testing: A Solution of Graphical Object Verification / J. Takahashi, Y. Kakuda 284

Session 6 Special Session

Test Strategies and Case Studies for SoC in Industries

At-Speed Built-in Test for Logic Circuits with Multiple Clocks / K. Hatayama, M. Nakao, Y. Sato 292

A Test Point Insertion Method to Reduce the Number of Test Patterns / M. Yoshimura, T. Hosokawa, M. Ohta 298

A SoC Test Strategy Based on a Non-scan DFT Method / H. Date, T. Hosokawa, M. Muraoka 305

Embedded Test Solution as a Breakthrough in Reducing Cost of Test for System on Chips / K. Iijima, A. Akar, C. McDonald, D. Burek 311

Manufacturing Test of SoCs / R. Kapur, T. Williams 317

Recent Advances in Test Planning for Modular Testing of Core-Based SoCs / V. Iyengar, K. Chakrabarty, E. Jan Marinissen 320

Session 7A Test Power Reduction

A Method to Reduce Power Dissipation during Test for Sequential Circuits / Y. Higami, S.-Y. Kobayashi, Y. Takamatsu 326

Test Power Optimization Techniques for CMOS Circuits / Z. Luo, X. Li, H. Li, S. Yang, Y. Min 332

Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling / K.-J. Lee, J.-J. Chen 338

Session 7B System-on-Chip Testing 1

A Simple Wrapped Core Linking Module for SoC Test Access / J. Song, S. Park 344

Testing System-on-Chip by Summations of Cores' Test Output Voltages / K. Ko, M. Wong, Y. Lee 350

Test Scheduling of BISTed Memory Cores for SoC / C.-W. Wang, J.-R. Huang, Y.-F. Lin, K.-L. Cheng, C.-T. Huang, C.-W. Wu 356

Session 7C Verification and Simulation

Effective Error Diagnosis for RTL Designs in HDLs / T.-Y. Jiang, C.-N. Liu, J.-Y. Jou 362

Evolutionary Test Program Induction for Microprocessor Design Verification / F. Corno, G. Cumani, M. Reorda, G. Squillero 368

Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models / S. Mirkhani, M. Lavasani, Z. Navabi 374

Session 8A Test Systems

Testing Embedded Systems by Using a C[superscript ++] Script Interpreter / H. Zainzinger 380

Extending EDA Environment from Design to Test / R. Rajsuman 386

Vector Memory Expansion System for T33xx Logic Tester / K. Yamada, Y. Takahashi 392

Session 8B System-on-Chip Testing 2

Integrated Test Scheduling, Test Parallelization and TAM Design / E. Larsson, K. Arvidsson, H. Fujiwara, Z. Peng 397

Core - Clustering Based SoC Test Scheduling Optimization / Y. Huang, S. Reddy, W.-T. Cheng 405

Test Scheduling and Test Access Architecture Optimization for System-on-Chip / H.-S. Hsu, J.-R. Huang, K.-L. Cheng, C.-W. Wang, C.-T. Huang, C.-W. Wu, Y.-L. Lin 411

Session 8C Current Testing

CMOS Floating Gate Defect Detection Using I[subscript DDQ] Test with DC Power Supply Superposed by AC Component / H. Michinishi, T. Yokohira, T. Okamoto, T. Kobayashi, T. Hondo 417

Test Time Reduction for I[subscript DDQ] Testing by Arranging Test Vectors / H. Yotsuyanagi, M. Hashizume, T. Tamesada 423

Time Slot Specification Based Approach to Analog Fault Diagnosis Using Built-in Current Sensors and Test Point Insertion / S. Upadhyaya, J. Lee, P. Nair 429

Call for Papers of ATS'03 437.

Notes:

"IEEE Computer Society Order Number PR01825"--T.p. verso.

Includes bibliographical references and author index.

ISBN:

0769518257

9780769518251

OCLC:

51162377

Access Restriction:

Restricted for use by site license.