Proceedings. IEEE Computer Society Annual Symposium on VLSI : new trends and technologies for VLSI systems design : ISVLSI 2003 : 20-21 February 2003, Tampa, Florida / edited by Asim Smailagic and Nagarajan Ranganathan ; sponsored by the IEEE Computer Society Technical Committee on VLSI.

Format:

Book

Conference/Event

Contributor:

Smailagic, Asim, 1950-

Ranganathan, N., 1961-

IEEE Xplore (Online service)

IEEE Computer Society. Technical Committee on VLSI.

Conference Name:

IEEE Computer Society Symposium on VLSI (2003 : Tampa, Fla.)

Language:

English

Subjects (All):

Integrated circuits--Very large scale integration--Design and construction--Congresses.

Integrated circuits.

Integrated circuits--Very large scale integration--Design and construction.

Computers--Circuits--Design and construction--Congresses.

Computers.

System design--Congresses.

System design.

Computers--Circuits--Design and construction.

Computers--Circuits.

Genre:

Conference papers and proceedings.

Physical Description:

xiv, 284 pages : illustrations

Other Title:

IEEE Computer Society Annual Symposium on VLSI 2003

New trends and technologies for VLSI systems design

ISVLSI 2003

VLSI, 2003, proceedings, IEEE Computer Society Annual Symposium on.

Place of Publication:

Los Alamitos, CA : IEEE Computer Society, 2003.

System Details:

Mode of access: World Wide Web.

text file

Contents:

Emerging Trends in VLSI Systems

Toward Design Technology in 2020: Trends, Issues, and Challenges / J. E. Harlow III 3

Challenges in VLSI Design / J. Fortes 5

Networks-on-Chip: The Quest for On-Chip Fault-Tolerant Communication / R. Marculescu 8

Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools / S. Das, A. Chandrakasan, R. Reif 13

Bouncing Threads: Merging a New Execution Model into a Nanotechnology Memory / S. E. Frost, A. F. Rodrigues, C. A. Giefer, P. M. Kogge 19

Advanced VLSI Design

Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS / K. K. Das, R. B. Brown 29

Power Comparison of Throughput Optimized IC Busses / E. Malley, A. Salinas, K. Ismail, L. Pileggi 35

LALM: A Logic-Aware Layout Methodology to Enhance the Noise Immunity of Domino Circuits / Y. Im, K. Roy 45

VLSI Circuits and Systems

Interconnect Effort

A Unification of Repeater Insertion and Logical Effort / S. Srinivasaraghavan, W. Burleson 55

Modified Sakurai-Newton Current Model and Its Applications to CMOS Digital Circuit Design / Makram M. Mansour, Mohammad M. Mansour, A. Mehrotra 62

A Fine-Grain Phased Logic CPU / R. B. Reese, M. A. Thornton, C. Traver 70

An Efficient Calibration Technique for Systematic Current-Mismatch of D/A Converters / K.-H. Baek, M.-J. Choe, S.-M. Kang 80

System-on-a-Chip Design

Energy Benefits of a Configurable Line Size Cache for Embedded Systems / C. Zhang, F. Vahid, W. Najjar 87

Reconfigurable Fast Memory Management System Design for Application Specific Processors / S. K. Agun, M. Chang 92

System Level Design

System Design Approach to Power Aware Mobile Computers / J. Warren, T. Martin, A. Smailagic, D. P. Siewiorek 101

Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable System-on-Chip (CSoC) / J. Becker, M. Vorbach 107

A Framework for Security on NoC Technologies / C. H. Gebotys, R. J. Gebotys 113

Low Power VLSI System Design I

Peak Power Minimization through Datapath Scheduling / S. P. Mohanty, N. Ranganathan, S. K. Chappidi 121

Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch / J. S. Hu, N. Vijaykrishnan, M. J. Irwin, M. Kandemir 127

Energy Recovering ASIC Design / C. H. Ziesler, J. Kim, M. C. Papaefthymiou 133

A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors / Y. Bai, R. I. Bahar 139

Low Power VLSI System Design II

An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages / R. Bai, S. Kulkarni, W. Kwong, A. Srivastava, D. Sylvester, D. Blaauw 149

Low Power Test Set Embedding Based on Phase Shifters / M. Bellos, D. Kagaris, D. Nikolos 155

Supply Voltage Scalable System Design Using Self-Timed Circuits / W. Kuang, J. S. Yuan, A. Ejnioui 161

Optimal Shielding/Spacing Metrics for Low Power Design / R. Arunachalam, E. Acar, S. R. Nassif 167

An O(N) Supply Voltage Assignment Algorithm for Low-Energy Serially Connected CMOS Modules and a Heuristic Extension to Acyclic Data Flow Graphs / A. U. Diril, Y. S. Dhillon, K. Choi, A. Chatterjee 173

Physical Design, Synthesis and Optimization

Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization / A. B. Kahng, B. Liu 183

Crosstalk Noise Analysis in Ultra Deep Submicrometer Technologies / M. A. Elgamel, K. S. Tharmalingam, M. A. Bayoumi 189

Block-Wise Extraction of Rent's Exponents for an Extensible Processor / T. Ahonen, T. Nurmi, J. Nurmi, J. Isoaho 193

A Novel Technique for Noise-Tolerance in Dynamic Circuits / S. Goel, T. Darwish, M. Bayoumi 203

Efficient VLSI Implementation of a VLC Decoder for Universal Variable Length Code / S. Xue, B. Oelmann 207

The Area-Efficient Euclidean Algorithm Block for Reed-Solomon Decoder / H. Lee 209

An Architectural Leakage Power Simulator for VHDL Structural Datapaths / C. Gopalakrishnan, S. Katkoori 211

Systolic Array Implementation of Block Based Hopfield Neural Network for Pattern Association / M.-J. Seow, H. Ngo, V. Asari 213

Pre-Computation of Rotation Bits in Unidirectional CORDIC for Trigonometric and Hyperbolic Computations / S. Ravichandran, V. Asari 215

Self-Timed Design with Dynamic Domino Circuits / J.-L. Yang, E. Brunvand 217

Hardware-Only Compression to Reduce Cost and Improve Utilization of Address Buses / J. Liu, N. R. Mahapatra, K. Sundaresan 220

Automated Dynamic Memory Data Type Implementation Exploration and Optimization / M. Leeman, C. Ykman, D. Atienza, V. De Florio, G. Deconinck 222

Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects / P. Larsson-Edefors, D. Eckerbert, H. Eriksson, L. J. Svensson 225

Decoder-Based Multi-Context Interconnect Architecture / A. Lodi, L. Ciccarelli, A. Cappelli, F. Campi, M. Toma 231

Titan II: An IPComp Processor for 10Gbit/sec Networks / I. Papaefstathiou 234

Frequency Domain Approach for CMOS Ultra-Wideband Radios / H.-J. Lee, D. S. Ha 236

Getting High-Performance Silicon from System-Level Design / W. R. Davis 238

Testable Sequential Circuit Design: Partitioning for Pseudoexhaustive Test / B. Shaer, K. Aurangabadkar, N. Agarwal 244

Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering / S. Ghosh, S. Basu, N. A. Touba 246

Hardware Implementation of Data Compression Algorithms for Memory Energy Optimization / L. Benini, D. Bruni, A. Macii, E. Macii 250

Dynamic Coding Technique for Low-Power Data Bus / M. Madhu, V. S. Murty, V. Kamakoti 252

Fast and Precise Power Prediction for Combinational Circuits / H. Li, J. K. Antonio, S. K. Dhall 254

High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders / J. Di, J. S. Yuan, R. Demara 260

Code Compression Techniques for Embedded Systems and Their Effectiveness / K. Sundaresan, N. R. Mahapatra 262

Random Characterization of Design Automation Algorithms / S. K. Kondapuram, P. M. Maurer 264

Layout-Aware Analog System Synthesis Based on Symbolic Layout Description and Combined Block Parameter Exploration, Placement and Global Routing / H. Tang, H. Zhang, A. Doboli 266

Equalizing Filter Design for Crosstalk Cancellation / J. Ren, M. Greenstreet 272

Behavioral Simulation of Power Line Noise Coupling in Mixed-Signal Systems Using SystemC / J. Lundgren, B. Oelmann, T. Ytterdal, P. Eriksson, M. Abdalla, M. O'Nils 275

Enhanced Techniques for Current Balanced Logic in Mixed-Signal ICs / L. Yang, J. S. Yuan 278

Quantum Voltage Comparator for 0.07 [mu]m CMOS Flash A/D Converters / J. Yoo, K. Choi, J. Ghaznavi 280.

Notes:

Includes bibliographical references and index.

ISBN:

0769519040

9780769519043

OCLC:

51785367

Access Restriction:

Restricted for use by site license.