Sixth IEEE International High-Level Design Validation and Test Workshop. proceedings : 7-9 November, 2001 / sponsored by IEEE Computer Society Technical Council on Test Technology, IEEE Computer Society Technical Committee on Design Automation.

Format:

Book

Conference/Event

Contributor:

IEEE Xplore (Online service)

IEEE Computer Society. Technical Council on Test Technology.

IEEE Computer Society. Design Automation Technical Committee.

Conference Name:

IEEE International High-Level Design Validation and Test Workshop (6th : 2001 : Monterey, Calif.)

Language:

English

Subjects (All):

Computer software--Verification--Congresses.

Computer software.

Computer software--Verification.

Electronic circuits--Testing--Congresses.

Electronic circuits.

Electronic digital computers--Evaluation--Congresses.

Electronic digital computers.

Electronic digital computers--Evaluation.

Electronic circuits--Testing.

Genre:

Conference papers and proceedings.

Physical Description:

x, 183 pages : illustrations

Other Title:

HLDVT'01

High-Level Design Validation and Test Workshop, 2001, proceedings, IEEE International.

Place of Publication:

Los Alamitos, Calif. : IEEE Computer Society, [2001]

System Details:

Mode of access: World Wide Web.

text file

Contents:

Session 1 Design Validation of Microprocessors

Relating Buffer-Oriented Microarchitecture Validation to High-Level Pipeline Functionality / N. Utamaphethai, R.D. Blanton, J.P. Shen 3

Automatic Validation of Pipeline Specifications / P. Mishra, N. Dutt, A. Nicolau 9

Automatic Test Generation for Micro-Architectural Verification of Configurable Microprocessor Cores with User Extensions / N. Bhattacharyya, A. Wang 14

Session 2 Techniques for High Level Design Validation and Test

Integrating Perl, Tcl and C++ into Simulation-Based ASIC Verification Environments / M.D. McKinney 19

Symbolic Simulation Heuristics for High-Level Design Descriptions with Uninterpreted Functions / K. Hamaguchi 25

Estimating the Relative Single Stuck-at Fault Coverage of Test Sets for a Combinational Logic Block from its Functional Description / I. Pomeranz, S.M. Reddy 31

Session 3 Invited Session: State-of-the-Art Formal Verification Techniques

Practical Use of Sequential ATPG for Model Checking: Going the Extra Mile Does Pay Off / M. Hsiao, J. Jain 39

Advanced SAT Techniques / S. Malik, L. Zhang

Symbolic Simulation Techniques

State-of-the-Art and Applications / C. Blank, H. Eveking, J. Levihn, G. Ritter 45

Session 4 Short Papers: High Level Verification and Analysis

A Model Checking Approach to Evaluating System Level Dynamic Power Management Policies for Embedded Systems / S.K. Shukla, R.K. Gupta 53

RTL Functional Verification Using Excitation and Observation Coverage / B. Min, G. Choi 58

Improving Test Quality through Resource Reallocation / A. Adir, E. Marcus, M. Rimon, A. Voskoboynik 64

Taylor Expansion Diagrams: A New Representation for RTL Verification / M. Ciesielski, P. Kalla, Z. Zeng, B. Rouzeyre 70

Session 5 Short papers: High Level Timing Verification and Testing

Fast Timed Cosimulation of HW/SW Implementation of Embedded Multiprocessor SoC Communication / S. Yoo, G. Nicolescu, L. Gauthier, A.A. Jerraya 79

Test Pattern Generation for Timing-Induced Functional Errors in Hardware-Sofware Systems / S. Arekapudi, F. Xin, J. Peng, I.G. Harris 83

Combining Complex Event Models and Timing Constraints / M. Jersak, K. Richter, R. Ernst 89

Using Live Sequence Charts for Hardware Protocol Specification and Compliance Verification / A. Bunker, G. Gopalakrishnan 95

Session 6 Verification of Real Life Designs

Proving Sequential Consistency by Model Checking / T. Braun, A. Condon, A.J. Hu, K.S. Juse, M. Laza, M. Leslie, R. Sharma 103

Experience with Term Level Modeling and Verification of the M*CORE Microprocessor Core / S. Lahiri, C. Pixley, K. Albin 109

Formal Verification of the Pentium 4 Multiplier / R. Kaivola, N. Narasimhan 115

Session 7 High-Level Specification and Verification

Reducing Bitvector Satisfiability Problems to Scale Down Design Sizes for RTL Property Checking / P. Johannsen 123

Constraints Specification at Higher Levels of Abstraction / F. Balarin, J. Burch, L. Lavagno, Y. Watanabe, R. Passerone, A. Sangiovanni-Vincentelli 129

A Language Formalism for Verification of PowerPC Custom Memories Using Compositions of Abstract Specifications / J. Bhadra, A. Martin, J. Abraham, M. Abadir 134

Session 8 High-Level Test Generation and Coverage Analysis

On Generation of the Minimum Pattern Set for Data Path Elements in SoC Design Verification Based on Port Order Fault Model / C-Y. Wang, S-W. Tung, J-Y. Jou 145

Hardware-Software Covalidation: Fault Models and Test Generation / I.G. Harris 151

Observability Enhanced Coverage Analysis of C Programs for Functional Validation / F. Fallah, I. Ghosh 157

Session 9 Improved Techniques for Boolean Reasoning

Using Cutwidth to Improve Symbolic Simulation and Boolean Satisfiability / D. Wang, E. Clarke, Y. Zhu, J. Kukula 165

An Enhanced Cut-Points Algorithm in Formal Equivalence Verification / Z. Khasidashvili, J. Moondanos, D. Kaiss, Z. Hanna 171

An Analysis of ATPG and SAT Algorithms for Formal Verification / G. Parthasarathy, C-Y. Huang, K-T. Cheng 177.

Notes:

"IEEE Computer Society Order Number PR01411"--T.p. verso.

ISBN:

0769514111

9780769514116

OCLC:

48500709

Access Restriction:

Restricted for use by site license.