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Innovative architecture for future generation high-performance processors and systems. 18-19 January, 2001, Maui, Hawaii / edited by Alex Veidenbaum, Kazuki Joe ; sponsored by DARPA/ITO PAC/C Program, Maui High-Performance Computing Center.
- Format:
- Book
- Conference/Event
- Conference Name:
- International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (2001 : Maui, Hawaii)
- Language:
- English
- Subjects (All):
- Computer architecture--Congresses.
- Computer architecture.
- High performance computing--Congresses.
- High performance computing.
- High performance processors--Congresses.
- High performance processors.
- Genre:
- Conference papers and proceedings.
- Physical Description:
- vii unnumbered pages, 109 pages : illustrations
- Other Title:
- Innovative architecture for future generation high-performance processors and systems, 2001.
- Place of Publication:
- Los Alamitos, Calif. : IEEE Computer Society, [2000]
- System Details:
- Mode of access: World Wide Web.
- text file
- Contents:
- Low-Power System Design
- Cache-In-Memory / J. Zawodny, P. Kogge 3
- Power Efficient Instruction Cache for Wide-Issue Processors / A.-M. Badulescu, A. Veidenbaum 12
- Power Reduction in Superscalar Datapaths through Dynamic Bit-Slice Activation / D. Ponomarev, G. Kucuk, K. Ghose 16
- Architectural and Compiler Strategies for Dynamic Power Management in the Copper Project / A. Azevedo, R. Cornea, I. Issenin, R. Gupta, N. Dutt, A. Nicolau, A. Veidenbaum 25
- Memory Hierarchy
- An Approach towards an Analytical Characterization of Locality and Its Portability / G. Bilardi, E. Peserico 37
- Pipelined Memory Hierarchies: Scalable Organizations and Application Performance / G. Bilardi, K. Ekanadham, P. Pattnaik 45
- Cache Coherence Protocol for Home Proxy Cache on RHiNET and Its Preliminary Performance Estimation / H. Nakajo, M. Ishii, J. Yamamoto, T. Kudo, Tomonori, Yokoyama, J.-i. Tsuchiya, H. Amano 53
- Compilers/Operating Systems
- Characteristics of Loop Unrolling Effect: Software Pipelining and Memory Latency Hiding / S. Hiroyuki, Y. Teruhiko 63
- Wrapped System Call in Communication and Execution Fusion OS: Cefos / H. Nakayama, T. Tanabayashi, M. Amamiya 73
- An Efficient Algorithm for Pointer-to-Array Access Conversion for Compiling and Optimizing DSP Applications / R. van Engelen, K. Gallivan 80
- High-Performance Systems
- Present Status of Development of the Earth Simulator / M. Yokokawa 93
- An Architecture of On-Chip-Memory Multi-Threading Processor / T. Matsuzaki, H. Tomiyasu, M. Amamiya 100.
- Notes:
- "The meeting took place at the Maui High-Performance Computing Center in January of 2001"--Pref.
- "IEEE Computer Society Press Order Number PR01309"--T.p. verso.
- Includes bibliographical references and index.
- ISBN:
- 0769513093
- 9780769513096
- 0769513107
- 9780769513102
- 0769513115
- 9780769513119
- OCLC:
- 48157915
- Access Restriction:
- Restricted for use by site license.
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