Proceedings. 20th IEEE VLSI Test Symposium : (VTS 2002) : 28 April - 2 May 2002, Monterey, California / sponsored by IEEE Computer Society Test Technology Technical Council.

Format:

Book

Conference/Event

Contributor:

IEEE Xplore (Online service)

IEEE Computer Society. Test Technology Technical Committee.

Institute of Electrical and Electronics Engineers.

Conference Name:

IEEE VLSI Test Symposium (20th : 2002 : Monterey, Calif.)

Language:

English

Subjects (All):

Integrated circuits--Very large scale integration--Testing--Congresses.

Integrated circuits.

Integrated circuits--Very large scale integration--Testing.

Genre:

Conference papers and proceedings.

Physical Description:

xxxvii, 452 pages : illustrations

Other Title:

VTS 2002

VLSI Test Symposium, 2002, (VTS 2002), proceedings 20th IEEE.

Place of Publication:

Los Alamitos, Calif. : IEEE Computer Society, [2002]

System Details:

Mode of access: World Wide Web.

text file

Contents:

Plenary Address: Business and Technical Challenges for Testing the Ghz Age / Jai K. Hakhu, Vice President xxxvii

Session 1 Microprocessor Test / Moderator: M. d'Abreau, Moderator: T. Mak

Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC Instruction Set Architecture / N. Tendolkar, R. Raina, R. Woltenberg, X. Lin, B. Swanson, G. Aldrich 3

Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs / A. Pandey, J. Patel 9

Scan Islands

A Scan Partitioning Architecture and Its Implementation on the Alpha 21364 Processor / D. Bhavsar, R. Davies 16

Session 2 Applications of Very Low Voltage and Slow Speed Testing / Moderator: K. Eshraghian, Moderator: P. Sidorowicz

Very Low Voltage Testing of SOI Integrated Circuits / E. MacDonald, N. Touba 25

Performance Comparison of VLV, ULV, and ECR Tests / W. Jiang, E. Peterson 31

Experimental Results for Slow-Speed Testing / C.-W. Tseng, J. Li, E. McCluskey 37

IP Session 1 Innovations in Test Automation

Innovations in Test Automation / Moderator: J. Borel, Organizer: Anand Raghunathan, Presenter: Jim Sproch, Presenter: Michael Howells, Presenter: Janusz Rajski 43

Session 3 Advancements in Scan-Based Testing / Moderator: M. Lousberg, Moderator: K. Hatayama

Scan-Path with Directly Duplicated and Inverted Duplicated Registers / M. Goessel, A. Singh, E. Sogomonyan 47

An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits / A. El-Maleh, A. Al-Suwaiyan 53

Logic BIST and Scan Test Techniques for Multiple Identical Blocks / K. Arabi 60

Session 4 Burn-in Reduction or Alternatives / Moderator: K. Mandl, Moderator: E. Dupont

Statistical Post-Processing at Wafersort

An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies / R. Madge, M. Rehani, K. Cota, W. Daasch 69

Yield-Reliability Modeling: Experimental Verification and Application to Burn-in Reduction / T. Barnett, A. Singh, M. Grady, K. Purdy 75

Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-Based I[subscript DDQ] Testing for Burn-in Reduction / S. Sabade, D. Walker 81

IP Session 2 DFT Testers 1

A Successful DFT Tester: What Will It Look Like? Is Revolution in Test Approaches Required? / Organizer: Lee Song, Presenter: Rudy Garcia, Presenter: Andrew Levy, Presenter: Don Wheater 87

Session 5 Test Set Compression Techniques / Moderator: K. Butler, Moderator: A. Rubio

How Effective Are Compression Codes for Reducing Test Data Volume? / A. Chandra, K. Chakrabarty, R. Medina 91

Test Vector Compression Using EDA-ATE Synergies / A. Khoche, E. Volkerink, J. Rivoir, S. Mitra 97

On Test Data Volume Reduction for Multiple Scan Chain Designs / S. Reddy, K. Miyase, S. Kajihara, I. Pomeranz 103

Session 6 Analog BIST / Moderator: J. da Franca, Moderator: S. Seth

Spectrum-Based BIST in Complex SoCs / G. Kasturirangan, M. Hsiao 111

A Self Calibrated ADC BIST Methodology / H.-K. Chen, C.-H. Wang, C.-C. Su 117

Self-Testing Second-Order Delta-Sigma Modulators Using Digital Stimulus / C.-K. Ong, K.-T. Cheng 123

IP Session 3 DFT Testers 2

A Successful DFT Tester: What Will It Look Like? Is DFT Tester a Logical Next Step in ATE Evolution? / Moderator: B. Bottoms, Organizer: Lee Song, Presenter: Paul Patton, Presenter: Wilhelm Radermacher, Presenter: Lee Song 129

Session 7 Increased Efficiency Testing / Moderator: B. Pouya, Moderator: P. Nagvajara

Testing High-Speed SoCs Using Low-Speed ATEs / M. Nourani, J. Chin 133

Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs / M. Iyer, K.-T. Cheng 139

On Using Efficient Test Sequences for BIST / R. David, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel 145

Session 8 Controlling and Reducing Test Power / Moderator: A. Crouch, Moderator: B. Kim

Controlling Peak Power during Scan Testing / R. Sankaralingam, N. Touba 153

Test Vector Modification for Power Reduction during Scan Testing / S. Kajihara, K. Ishida, K. Miyase 160

Test Power Reduction through Minimization of Scan Chain Transitions / O. Sinanoglu, I. Bayraktaroglu, A. Orailoglu 166

Wireless Test / Organizer: Robert Aitken, Presenter: Mustapha Slamani, Presenter: H. Ding, Presenter: William R. Eisenstadt, Presenter: Sanghoon Choi, Presenter: John McLaughlin 173

Analog & Mixed Signal BIST: Too Much, Too Little, Too Late? / Moderator: Adam Osseiran, Organizer: William DeWilkins, Panelist: Barry Baril, Panelist: William DeWilkins, Panelist: Fidel Muradali, Panelist: Ken Posse, Panelist: Lee Song, Panelist: Sassan Tabatabaei 175

Test as a Key Enabler for Faster Yield Ramp-Up / Moderator: Julie Segal, Organizer: Rene Segers, Panelist: R. Aitken, Panelist: S. Eichenberger, Panelist: A. Gattiker, Panelist: M. Millegen, Panelist: R. Segers, Panelist: S. Venkataraman 177

Session 9 Diagnosis / Moderator: F. Maamari, Moderator: C. Metra

Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits / M. Amyeen, I. Pomeranz, W. Fuchs 181

Diagnosis of Sequence-Dependent Chips / J. Li, E. McCluskey 187

Speeding up the Byzantine Fault Diagnosis Using Symbolic Simulation / S.-Y. Huang 193

Session 10 Analog Circuit Testing / Moderator: J. Abraham, Moderator: R. Velasco

Filters Designed for Testability Wrapped on the Mixed-Signal Test Bus / J. Calvano, V. Alves, M. Lubazewski, A. Mesquita 201

Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division / T. Yamaguchi, M. Soma, L. Malarsie, M. Ishida, H. Musha 207

Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis / S. Ozev, A. Orailoglu 213

Session 11 High Level Test Techniques / Moderator: J. Aylor, Moderator: J. Reynick

Instruction-Based Self-Testing of Processor Cores / N. Kranitis, D. Gizopoulos, A. Paschalis, Y. Zorian 223

An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation / L. Berrojo, F. Corno, L. Entrena, I. Gonzalez, C. Lopez, M. Sonza Reorda, G. Squillero 229

Program Slicing for Hierarchical Test Generation / V. Vedula, J. Abraham, J. Bhadra 237

Session 12 SoC Test Infrastructure / Moderator: M. Mowji, Moderator: L. Basto

Design for Testability and Testing of IEEE 1149.1 Tap Controller / S. Mitra, E. McCluskey, S. Makar 247

On Using Rectangle Packing for SoC Wrapper/TAM Co-optimization / V. Iyengar, K. Chakrabarty, E. Jan Marinissen 253

Cluster-Based Test Architecture Design for System-on-Chip / S. Goel, E. Jan Marinissen 259

IP Session 5 Multi-GigaHertz Testing Challenges and Solutions

Multi-GigaHertz Testing Challenges and Solutions / Organizer: Karim Arabi, Presenter: Klaus-Dieter Hilliges, Presenter: David Keezer, Presenter: Sassan Tabatabaei 265

Session 13 Test Tools and Algorithms / Moderator: T. Williams, Moderator: J. Segura

Exploiting Dominance and Equivalence Using Fault Tuples / K. Dwarakanath, R. Blanton 269

Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? / N. Krishnamurthy, J. Bhadra, M. Abadir, J. Abraham 275

RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics / K.-L. Cheng, J.-C. Yeh, C.-W. Wang, C.-T. Huang, C.-W. Wu 281

Session 14 Supply Current Testing / Moderator: T. Storey, Moderator: R. Rajsuman

Eigen-Signatures for Regularity-Based I[subscript DDQ] Testing / Y. Okuda 289

Speeding-up I[subscript DDQ] Measurements / C. Thibeault 295

Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform / S. Bhunia, K. Roy 302

IP Session 6 IEEE P1500 in Practice / Moderator: R. Kapur, Organizer: Yervant Zorian, Presenter: Teresa McLaurin, Presenter: Yervant Zorian, Presenter: Erik Jan Marinissen

Debating the Future of Burn-In / Moderator: Edward J. McCluskey, Organizer: Subhasish Mitra, Panelist: Bob Madge, Panelist: Peter Maxwell, Panelist: Phil Nigh, Panelist: Mike Rodgers 311

Special Session 4 Hot Topic

Beyond CMOS / Organizer: B. Courtois, Presenter: M. Forshaw 315

Special Session 5 Embedded Tutorial

Challenges of Mixed-Signal Board Design and Test / G. Roberts 317

Session 15 Test Pattern Generation / Moderator: J. Hayes, Moderator: L. Bouzaida

A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits / S. Ohtake, S. Miwa, H. Fujiwara 321

A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits / T. Hosokawa, H. Date, M. Muraoka 328

Test Pattern Generation for Signal Integrity Faults on Long Interconnects / A. Attarha, M. Nourani 336

Session 16 Tester Hardware Modeling and Improvements / Moderator: M. Topsakal, Moderator: F. Lombardi

Improved Test Monitor Circuit in Power Pin DfT / R. Schuttert, F. de Jong, B. Kup 345

Measuring Stray Capacitance on Tester Hardware / A. Halder, P. Variyam, A. Chatterjee, J. Ridley 351

Power Supply Transient Signal Analysis under Real Process and Test Hardware Models / A. Singh, J. Plusquellic, A. Gattiker 357

IP Session 7 FPGA Test Practices / Organizer: Yervant Zorian, Organizer: Virage Logic, Moderator: Michel Renovell, Presenter: M. Abramovici, Presenter: C. Stroud, Presenter: S. Toutounchi, Presenter: A. Lai

Session 17 Fault Modeling & Extraction / Moderator: G. Robinson, Moderator: S. Mourad

Layout Analysis to Extract open Nets Caused by Systematic Failure Mechanisms / S. Chakravarty, K. Komeyli, E. Savage, M. Carruthers, B. Stastny, S. Zachariah 367

Fault Models for Speed Failures Caused by Bridges and Opens / S. Chakravarty, A. Jain 373

Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits / R. Kundu, R. Blanton 379

Session 18 Memory Testing / Moderator: N. Saxena, Moderator: S. Shoukourian

Testing and Diagnosing Embedded Content Addressable Memories / J.-F. Li, R.-S. Tzeng, C.-W. Wu 389

Testing Static and Dynamic Faults in Random Access Memories / S. Hamdioui, Z. Al-Ars, Ad J. van de Goor 395

Approximating Infinite Dynamic Behavior for DRAM Cell Defects / Z. Al-Ars, Ad J. van de Goor 401

IP Session 8

Validation & Test of Network Processors and ASICs / Moderator: C.-H. Chiang, Organizer: Sujit Dey, Presenter: Faraydon Karim, Presenter: Haluk Konuk, Presenter: Keesup Kim 407

Session 19 Test-Cost Reduction / Moderator: D. Edenfeld, Moderator: R. Pendurkar

Test Economics for Multi-site Test with Modern Cost Reduction Techniques / E. Volkerink, A. Khoche, J. Rivoir, K. Hilliges 411

LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects / K. Sekar, S. Dey 417

Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions / P. Gonciari, B. Al-Hashimi, N. Nicolici 423

Session 20 Oscillation - Based Test / Moderator: B. Kaminska, Moderator: B. Straube

Practical Solutions for the Application of the Oscillation-Based-Test: Start-up and On-Chip Evaluation / D. Vazquez, G. Huertas, G. Leger, A. Rueda, J. Huertas 433

Evaluation of the Oscillation-Based Test Methodology for Micro-Electro-Mechanical Systems / V. Beroulle, Y. Bertrand, L. Latorre, P. Nouet 439

Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer? / Moderator: Fidel Muradali, Organizer: Mike Ricchetti, Panelist: Bart Vermeulen, Panelist: Bulent Dervisoglu, Panelist: Bob Gottlieb, Panelist: Bernd Koenemann, Panelist: C.J. Clark 445

Special Session 7 Embedded Tutorial

Challenges in Nanometric Technology Scaling: Trends and Projections / Organizer: Jaume Segura, Presenter: Vivek De, Presenter: Ali Keshavarzi 447

SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow? / Moderator: S. Mir, Panelist: H. Bederr, Panelist: R.D. Blanton, Panelist: H. Kerkhoff, Panelist: H.J. Klim 449.

Notes:

"IEEE Computer Society Order Number PRO1570"--T.p. verso.

Includes bibliographical references and index.

ISBN:

0769515703

9780769515700

0769515711

9780769515717

076951572X

9780769515724

OCLC:

49752005

Access Restriction:

Restricted for use by site license.