IEEE European Test Workshop. proceedings : 23-26 May, 2000, Cascais, Portugal / sponsored by IEEE Computer Society Test Technology Technical Council (TTTC) ; in cooperation with Electrical and Computer Engineering Department, Lisbon Technical University ; organized by INESC.

Format:

Book

Conference/Event

Contributor:

IEEE Xplore (Online service)

IEEE Computer Society. Technical Council on Test Technology.

IEEE Computer Society.

Lisbon Technical University. Electrical and Computer Engineering Department.

Instituto Nacional de Estudios Sociales y Capacitación.

Conference Name:

IEEE European Test Workshop (2000 : Cascais, Portugal)

Language:

English

Subjects (All):

Integrated circuits--Testing--Congresses.

Integrated circuits.

Genre:

Conference papers and proceedings.

Physical Description:

xvi unnumbered pages, 181 pages : illustrations

Other Title:

ETW 2000

Place of Publication:

Los Alamitos, Calif. : IEEE Computer Society Press, [2000]

System Details:

Mode of access: World Wide Web.

text file

Contents:

Session 1A Delay Testing and Test Scheduling

Bridging the Testing Speed Gap: Design for Delay Testability / H. Speek, H. Kerkhoff, M. Sachdev, M. Shashaani 3

Delay Fault Testing: Choosing between Random SIC and Random MIC Test Sequences / A. Virazel, R. David, P. Girard, C. Landrault, S. Pravossoudovitch 9

Session 1B Scan and Functional Testing

Embedded Test and Debug of Full Custom and Synthesizable Microprocessor Cores / A. Burdass, G. Campbell, R. Grisenthwaite, D. Gwilt, P. Harrod, R. York 17

Session 2A System Testing

A New Compression/Decompression Method for Non-Correlated Test Patterns: Application to Test Pins Expansion / W. Maroufi

System-Level Test Bench Generation in a Co-Design Framework / M. Lajolo, L. Lavagno, M. Rebaudengo, M. Reorda, M. Violante 25

Session 3A I[subscript DDQ] Testing

LEAP: An Accurate Defect-Free I[subscript DDQ] Estimator / A. Ferre, J. Figueras 33

Defect Detection from Visual Abnormalities in Manufacturing Process Using I[subscript DDQ] / M. Sanada 39

Session 6A Analog and Mixed-Signal Testing

Static and Dynamic On-Chip Test Response Evaluation Using a Two-Mode Comparator / D. De Venuto, M. Ohletz, G. Matarrese 47

Towards an ADC BIST Scheme Using the Histogram Test Technique / F. Azais, S. Bernard, Y. Bertrand, M. Renovell 53

Session 6B Core-Based Testing

Practical Methods and Tools for Embedded Macro Test / B. Koenemann

Session 7A Fault Simulation and FPGA Testing

A Parameterizable Fault Simulator for Bridging Faults / P. Engelke, B. Becker, M. Keim 63

Hierarchical Defect-Oriented Fault Simulation for Digital Circuits / M. Blyzniuk, T. Cibakova, E. Gramatova, W. Kuzmicz, M. Lobur, W. Pleskacz, J. Raik, R. Ubar 69

Analyzing the Test Generation Problem for an Application-Oriented Test of FPGAs / M. Renovell, J. Portal, P. Faure, J. Figueras, Y. Zorian 75

Session 7B Challenges in Deep Sub-Micron Testing

Test Challenges in Nanometer Technologies / S. Kundu, S. Sengupta, R. Galivanche 83

Current Testing Procedure for Deep Submicron Devices / A. Chichkov, D. Merlier, P. Cox 91

Session 9A High Level Test

RTL-Based Functional Test Generation for High Defects Coverage in Digital SOCs / M. Santos, F. Goncalves, I. Teixeira, J. Teixeira 99

Combining Symbolic and Genetic Techniques for Efficient Sequential Circuit Test Generation / M. Boschini, X. Yu, F. Fummi, E. Rudnick 105

How to Avoid Random Walks in Hierarchical Test Path Identification / Y. Makris, J. Collins, A. Orailoglu 111

Session 9B Memory Testing

An Effective Distributed BIST Architecture for RAMs / M. Bodoni, A. Benso, S. Chiusano, S. Di Carlo, G. Di Natale, P. Prinetto 119

Compressed Bit Fail Maps for Memory Fail Pattern Classification / J. Vollrath, U. Lederer, T. Hladschik 125

Session 10A BIST and Concurrent Testing

A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis / D. Berthelot, M. Flottes, B. Rouzeyre 133

Low Cost Concurrent Test Implementation for Linear Digital Systems / I. Bayraktaroglu, A. Orailoglu 140

On the Use of Multiple Fault Detection Times in a Method for Built-In Test Pattern Generation for Synchronous Sequential Circuits / I. Pomeranz, S. Reddy 144

Session 10B Board Testing

A System Level Boundary Scan Controller Board for VME Applications / N. Cardoso, C. Almeida, J. da Silva 153

Session 11 BIST Architecture

Fast and Low-Area TPGs Based on T-Type Flip-Flops Can Be Easily Integrated to the Scan Path / T. Garbolino, A. Hlawiczka, A. Kristof 161

CA-CSTP: A New BIST Architecture for Sequential Circuits / F. Corno, M. Reorda, G. Squillero, M. Violante 167

Comparison of Defect Detection Capabilities of Current-Based and Voltage-Based Test Methods / B. Kruseman 175

IEEE 1149.4 Mixed-Signal Test Bus Standard / A. Osseiran.

Notes:

"ETW 2000"--Cover.

Includes bibliographical references and index.

ISBN:

0769507018

9780769507019

0769507026

9780769507026

0769507034

9780769507033

OCLC:

46473986

Access Restriction:

Restricted for use by site license.