Proceedings of the Ninth Asian Test Symposium. (ATS 2000) : December 4-6, 2000 Taipei, Taiwan / sponsored by the IEEE Computer Society Test Technology Technical Council (TTTC) ; co-sponsored by National Cheng-Kung University.

Format:

Book

Conference/Event

Contributor:

IEEE Xplore (Online service)

IEEE Computer Society. Test Technology Technical Committee.

Guo li Chenggong da xue.

Conference Name:

Asian Test Symposium (9th : 2000 : Taipei, Taiwan)

Language:

English

Subjects (All):

Electronic digital computers--Circuits--Testing--Congresses.

Electronic digital computers.

Electronic digital computers--Circuits--Testing.

Electronic circuits--Testing--Congresses.

Electronic circuits.

Fault-tolerant computing--Congresses.

Fault-tolerant computing.

Electronic circuits--Testing.

Genre:

Conference papers and proceedings.

Physical Description:

xxiii, 495 pages : illustrations

Other Title:

ATS 2000

Ninth Asian Test Symposium

Asian Test Symposium, 2000, (ATS 2000), proceedings of the Ninth.

Place of Publication:

Los Alamitos, Calif. : IEEE Computer Society, [2000]

System Details:

Mode of access: World Wide Web.

text file

Contents:

Keynote Address I Testing in the Fourth Dimension / Speaker: Vishwani D. Agrawal, Moderator: Kwang Ting (Tim) Cheng 2

Keynote Address II Challenges for the Academic Test Community / Speaker: Melvin A. Breuer, Moderator: Kwang Ting (Tim) Cheng 4

Industry Session I CAD Tools on Testing / Jing-Yang Jou

DFT and BIST Techniques for the Future / H.-P. Wang, J. Turino 6

DFT Closure / F. Hayat, T. Williams, R. Kapur, D. Hsu 8

Current Status and Future Trend on CAD Tools for VLSI Testing / W.-T. Cheng 10

Industry Session II Taiwan Test Industry: Value Added Testing in the New Millennium / Chung-Len Lee 13

Panel I Mixed-Signal SoC Testing: Is Mixed-Signal Design-for-Test on Its Way? / Moderator & Organizer: Chin-Long Wey, Panelists: Adam Osseiran, Jose Luis Huertas, Yeon-Chen Nieu 15

Panel II Collaboration between Industry and Academia in Test Research / Moderator & Organizer: Kwang Ting (Tim) Cheng, Panelists: Vishwani Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu 17

Session A1 Analog & Mixed Signal Test I / Kiyoshi Furuya

Test Generation for Fault Isolation in Analog Circuits Using Behavioral Models / S. Cherubal, A. Chatterjee 19

Fault Diagnosis for Linear Analog Circuits / J.-W. Lin, C.-L. Lee, C.-C. Su, J.-E. Chen 25

Testing Mixed-Signal Cores: Practical Oscillation-Based Test in an Analog Macrocell / G. Huertas, D. Vazquez, E. Peralias, A. Rueda, J. Huertas 31

New Built-in Self-Test Technique Based on Addition/Subtraction of Selected Node Voltages / K. Ko, M. Wong 39

Session A2 Memory Built-in Self-Test and Self-Diagnosis / Ad J. van de Goor

A Built-in Self-Test and Self-Diagnosis Scheme for Embedded SRAM / C.-W. Wang, C.-F. Wu, J.-F. Li, C.-W. Wu, T. Teng, K. Chiu, H.-P. Lin 45

An FPGA-Based Re-Configurable Functional Tester for Memory Chips / J.-R. Huang, C. Ong, K. Cheng, C.-W. Wu 51

BIST TPG for SRAM Cluster Interconnect Testing at Board Level / C.-H. Chiang, S. Gupta 58

Efficient Built-in Self-Test Algorithm for Memory / S.-J. Wang, C.-J. Wei 66

Session B1 Analog & Mixed Signal Test II / M.D. Shieh

Optimal Test-Set Generation for Parametric Fault Detection in Switched Capacitor Filters / W. Choi, R. Harjani, B. Vinnakota 72

TI-BIST: A Temperature Independent Analog BIST for Switched-Capacitor Filters / L. Carro, E. Cota, M. Lubaszewski, Y. Bertrand, F. Azais, M. Renovell 78

Analog Circuit Equivalent Faults in the D.C. Domain / M. Worsman, M. Wong, Y. Lee 84

A Methodology for Fault Model Development for Hierarchical Linear Systems / Y.-C. Huang, C.-L. Lee, J.-W. Lin, J.-E. Chen, C.-C. Su 90

Testing a PWM Circuit Using Functional Fault Models and Compact Test Vectors for Operational Amplifiers / J. Calvano, V. Alves, M. Lubaszewski 96

Session B2 Fault Simulation & Timing Simulation / Kazumi Hatayama

A New Framework for Static Timing Analysis, Incremental Timing Refinement, and Timing Simulation / L.-C. Chen, S. Gupta, M. Breuer 102

On the Feasibility of Fault Simulation Using Partial Circuit Descriptions / I. Pomeranz, S. Reddy 108

Fsimac: A Fault Simulator for Asynchronous Sequential Circuits / S. Sur-Kolay, M. Roncken, K. Stevens, P. Chaudhuri, R. Roy 114

Simulation of Resistive Bridging Fault to Minimize the Presence of Intermediate Voltage and Oscillation in CMOS Circuits / A. Keshk, Y. Miura, K. Kinoshita 120

Non-Invasive Timing Analysis of IBM G6 Microprocessor L1 Cache Using Picosecond Imaging Circuit Analysis / S. Polonsky, M. Mc Manus, D. Knebel, S. Steen, P. Sanda 125

Fringe Meeting: SoC Testing & P1500 Standard / Shianling Wu, Yervant Zorian, Participants: Xinghao Chen, Martin Fischer, Douglas Kay, J.C. Frank Lien, Rubin A. Parekhji, Phil Smith, L.T. Wang

Session C1 Fault Analysis I / Shiyi Xu

An Experimental Analysis of Spot Defects in SRAMs: Realistic Fault Models and Tests / S. Hamdioui, Ad J. van de Goor 131

Enhanced Untestable Path Analysis Using Edge Graphs / S. Kajihara, T. Shimono, I. Pomeranz, S. Reddy 139

A Waveform Simulator Based on Boolean Process / L. Li, X. Yu, C.-W. Wu, Y. Min 145

On the Superiority of DO-RE-ME/MPG-D over Stuck-at-Based Defective Part Level Prediction / J. Dworak, M. Grimaila, B. Cobb, T-C. Wang, Li-C. Wang, M. Mercer 151

Session C2 Test Generation I / Yukihiro Iguchi

Compaction-Based Test Generation Using State and Fault Information / A. Giani, S. Sheng, M. Hsiao, V. Agrawal 159

Test Sequence Compaction for Sequential Circuits with Reset States / Y. Higami, Y. Takamatsu, K. Kinoshita 165

SPIRIT: Satisfiability Problem Implementation for Redundancy Identification and Test Generation / E. Gizdarski, H. Fujiwara 171

Forecasting the Efficiency of Test Generation Algorithms for Digital Circuits / S. Xu, W. Cen 179

Session C3 Functional Testing / Tomoo Inoue

Fast Hierarchical Test Path Construction for DFT-Free Controller-Datapath Circuits / Y. Makris, J. Collins, A. Orailoglu 185

Faster Processing for Microprocessor Functional ATPG / J. Hirase, S. Yoshimura 191

Verification of Deadlock Free Property of High Level Robot Control / H. Hiraishi 198

Functional Testing of Microprocessors with Graded Fault Coverage / R. Kannah, C. Ravikumar 204

Session D1 Built-in Self-Test I / Jacob Savir

Single-Control Testability of RTL Data Paths for BIST / T. Masuzawa, M. Izutsu, H. Wada, H. Fujiwara 210

A BIST Methodology for At-Speed Testing of Data Communications Transceivers / S. Lin, S. Mourad, S. Krishnan 216

High-Speed Generation of LFSR Signatures / M.-D. Shieh, H.-F. Lo, M.-H. Sheu 222

Session D2 Software Testing & Test Synthesis / Wen-Ben Jone

Strong Self-Testability for Data Paths High-Level Synthesis / X. Li, T. Masuzawa, H. Fujiwara 229

Generating Test Items for Checking Illegal Behaviors in Software Testing / M. Hirayama, J. Okayasu, T. Yamamoto, O. Mizuno, T. Kikuno 235

Using Genetic Algorithms for Test Case Generation in Path Testing / J.-C. Lin, P.-L. Yeh 241

Session D3 Embedded-Core Testing / Douglas Kay

A Hierarchical Test Control Architecture for Core Based Design / K.-J. Lee, C.-I. Huang 248

Embedded Core Testing Using Genetic Algorithms / R. Xu, M. Hsiao 254

Functional Testing and Fault Analysis Based Fault Coverage Enhancement Techniques for Embedded Core Based Systems / A. Bagwe, R. Parekhji 260

Session E1 Memory Testing / Rubin A. Parekhji

Detection of SRAM Cell Stability by Lowering Array Supply Voltage / D.-M. Kwai, H.-W. Chang, H.-J. Liao, C.-H. Chiao, Y.-F. Chou 268

A Realistic Fault Model for Flash Memories / Y.-L. Horng, J.-R. Huang, T.-Y. Chang 274

Impact of Memory Cell Array Bridges on the Faulty Behavior in Embedded DRAMs / Z. Al-Ars, Ad J. van de Goor 282

Memory Test Time Reduction by Interconnecting Test Items / W.-J. Wu, C. Tang 290

An Efficient Parallel Transparent Diagnostic BIST / D. Huang, W.-B. Jone 299

Session E2 Test Generation II / Christian Landrault

Test Generation for Crosstalk-Induced Faults: Framework and Computational Results / W.-Y. Chen, S. Gupta, M. Breuer 305

Testing Programmable Interconnect Systems: An Algorithmic Approach / B. Liu, F. Lombardi, W. Huang 311

Reducing Test Application Time for Full Scan Circuits by the Addition of Transfer Sequences / I. Pomeranz, S. Reddy 317

TOF: A Tool for Test Pattern Generation Optimization of an FPGA Application-Oriented Test / M. Renovell, J. Portal, P. Faure, J. Figueras, Y. Zorian 323

Formal Verification of Data-Path Circuits Based on Symbolic Simulation / Y. Morihiro, T. Yoneda 329

Session E3 I[subscript DDQ] Testing / Sying-Jyan Wang

Is I[subscript DDQ] Testing not Applicable for Deep Submicron VLSI in Year 2011? / C.-W. Lu, C.-L. Lee, C.-C. Su, J.-E. Chen 338

High Speed I[subscript DDQ] Test and Its Testability for Process Variation / M. Hashizume, H. Yotsuyanagi, M. Ichimiya, T. Tamesada, M. Takeda 344

Memory Reduction of I[subscript DDQ] Test Compaction for Internal and External Bridging Faults / T. Maeda, K. Kinoshita 350

A High-Speed I[subscript DDQ] Sensor Implementation / Y. Antonioli, T. Inufushi, S. Nishikawa, K. Kinoshita 356

Cyclic Greedy Generation Method for Limited Number of I[subscript DDQ] Tests / T. Shinogi, M. Ushio, T. Hayashi 362

Session F1 Built-in Self-Test II / Shianling Wu

Accelerated Test Pattern Generators for Mixed-Mode BIST Environments / W.-L. Wang, K.-J. Lee 368

Effective Parallel Processing Techniques for the Generation of Test Data for a Logic Built-in Self Test System / P. Chang, B. Keller, S. Paliwal 374

Design and Testing of Fast and Cost Effective Serial Seeding TPGs Based on One-Dimensional Linear Hybrid Cellular Automata / A. Hlawiczka, M. Kopec 380

An Efficient BIST Design Using LFSR-ROM Architecture / L. Li, Y. Min 386

Session F2 Testability Analysis and Design for Testability / Xinghao Chen

Novel Techniques for Improving Testability Analysis / Y.-H. Su, C.-H. Cheng, S.-C. Chang 392

A Class of Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption / M. Inoue, E. Gizdarski, H. Fujiwara 398

Design for Sequential Testability: An Internal State Reseeding Approach for 100% Fault Coverage / M. Flottes, C. Landrault, A. Petitqueux 404

Session F3 Fault Tolerance / J.C. Frank Lien

Testing Approach within FPGA-Based Fault Tolerant Systems / A. Doumar, H. Ito 411

Transient-Fault Tolerant VHDL Descriptions: A Case-Study for Area Overhead Analysis / F. Vargas, A. Amory 417

Fault Tolerant Multistage Interconnection Networks with Widely Dispersed Paths / N. Kamiura, T. Kodera, N. Matsui 423

A Testable/Fault-Tolerant FFT Processor Design / S.-K. Lu, J.-S. Shih, C.-W. Wu 429

Session G1 Fault Analysis II / Mike Wong

Charge Sharing Fault Analysis and Testing for CMOS Domino Logic Circuits / C.-H. Cheng, W.-B. Jone, J.-S. Wang, S.-C. Chang 435

Testing Domino Circuits in SOI Technology / E. MacDonald, N. Touba 441

A Case Study of Failure Analysis and Guardband Determination for a 64M-Bit DRAM / C.-T. Kao, S. Wu, J.-E. Chen 447

Session G2 Low-Power Testing / C.P. Ravikumar

Peak-Power Reduction for Multiple-Scan Circuits during Test Application / K.-J. Lee, T.-C. Huang, J.-J. Chen 453

An Adjacency-Based Test Pattern Generator for Low Power BIST Design / P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch 459

Distribution-Graph Based Approach and Extended Tree Growing Technique in Power-Constrained Block-Test Scheduling / V. Muresan, X. Wang, V. Muresan, M. Vladutiu 465

Session G3 Self-Checking Circuits and Concurrent Fault Detection / Yinghua Min

A Method for Determining Whether Asynchronous Circuits Are Self-Checking / M. Liebelt, C.-C. Lim 472

On Testing Safety-Sensitive Digital Systems / J. Savir 478

Accumulation-Based Concurrent Fault Detection for Linear Digital State Variable Systems / I. Bayraktaroglu, A. Orailoglu 484

Tutorial 1 High Performance/Delay Testing / Moderator: Shi-Yu Huang, Coordinating Presenter: Sudhakar M. Reddy 490

Tutorial 2 SoC Testing and P1500 Standard / Moderator: Tsin-Yuan Chang, Coordinating Presenter: Yervant Zorian 492.

Notes:

"IEEE Computer Society Order Number PR00887"--T.p. verso.

Includes bibliographical references and author index.

ISBN:

0769508871

9780769508870

076950888X

9780769508887

0769508898

9780769508894

OCLC:

45475694

Access Restriction:

Restricted for use by site license.