13th Symposium on Integrated Circuits and Systems Design. proceedings : 18-24 September, 2000, Manaus, Brazil / edited by Ricardo Reis, Wilhelmus Van Noije, and José Carlos Monteiro ; sponsored by Brazilian Computer Society ; co-sponsored by International Federation for Information Processing, Brazilian Microelectronics Society ; organized by Federal University of Rio Grande do Sul ... [and others].

Format:

Book

Conference/Event

Contributor:

Reis, Ricardo A. L. (Ricardo Augusto da Luz)

Monteiro, José, 1966-

Noije, Wilhelmus Van.

IEEE Xplore (Online service)

Sociedade Brasileira de Computação.

International Federation for Information Processing.

Sociedade Brasileira de Microeletrônica.

Universidade Federal do Rio Grande do Sul.

Conference Name:

Simpósio de Concepção de Circuitos Integrados (13th : 2000 : Manaus, Brazil)

Language:

English

Subjects (All):

Integrated circuits--Computer-aided design--Congresses.

Integrated circuits.

Integrated circuits--Computer-aided design.

Genre:

Conference papers and proceedings.

Physical Description:

xiv, 404 pages : illustrations

Other Title:

Proceedings, 13th Symposium on Integrated Circuits and Systems Design

Thirteenth Symposium on Integrated Circuits and Systems Design

Symposium on Integrated Circuits and Systems Design

SBCCI 2000

Integrated Circuits and Systems Design, 2000, proceedings, 13th Symposium on.

Place of Publication:

Los Alamitos, Calif. : IEEE Computer Society, 2000.

System Details:

Mode of access: World Wide Web.

text file

Contents:

Session 1 Design for Test

Some Experiments in Test Pattern Generation for GPGA-Implemented Combinational Circuits / M. Renovell, J. Portal, P. Faure, J. Figueras, Y. Zorian 3

Solving the I/O Bandwidth Problem in System on a Chip Testing / W. Maroufi, M. Benabdenbi, M. Marzouki 9

Testability Properties of Vertex Precedent BDDs / A. Reis, A Prado, M. Lubaszewski 15

ATG-Based Timing Analysis of Circuits Containing Complex Gates / J. Guntzel, A. Pinto, E. d'Avila, R. Reis 21

Session 2 Microarchitectures

Architecture

A Bit Scalable Architecture for Fuzzy Processors with Three Inputs and a Flexible Fuzzification Unit / R. d'Amore 29

Partitioned Branch Condition Resolution Logic / A. Farooqui, K. Current, V. Oklobdzija 35

Synthesis of High Performance Extended Burst Mode Asynchronous State Machines / D. de Oliveira, M. Strum, W. Chau, W. Cunha 41

Improved IDEA / S. Salomao, J. Alcantara, V. Alves, F. Franca 47

Session 3 Logic Design

Revisiting Hamiltonian Decomposition of the Hypercube / K. Okuda, S. Song 55

An Input-Output Encoding Approach for Serial Decomposition / V. Muthukumar, R. Bignall, H. Selvaraj 61

Disjunctive Decomposition of Switching Functions Using Symmetry Information / M. Chrzanowska-Jeske, W. Wang, J. Xia, M. Jeske 69

Methods Based on Petri Net for Resource Sharing Estimation / P. Maciel, F. Filho, E. Barros, W. Rosenstiel 75

Session 4 Analog Design

Robust Implementation and Statistical Modeling of a VI-Converter / A. Graupner, R. Schuffny 83

Resizing Rules for the Reuse of MOS Analog Designs / C. Galup-Montoro, M. Schneider 89

Analysis and Design of a Family of Low-Power Class AB Operational Amplifiers / F. Silveira, D. Flandre 94

A Generator of Trapezoidal Association of Transistors (TAT): Improving Analog Circuits in a Pre-Diffused Transistor Array / A. Aita, S. Bampi, J. Choi 99

Session 5 High Level Synthesis

Address Satisfaction for Storage Files with Fifos or Stacks during Scheduling of DSP Algorithms / C. Pinto, K. van Eijk, B. Mesman, J. Jess 107

Register Binding for Predicated Execution in DSP Applications / Q. Zhao, C. van Eijk, C. Pinto, J. Jess 113

A Data Path Synthesis Method to Self-Testable Application Specific Integrated Circuit (ASIC) / J. Costa, J. Neto 119

From a Hyperdocument-Centric to an Object-Oriented Approach for the Cave Project / L. Indrusiak, R. Reis 125

Session 6 Physical Design

WTROPIC: A WWW-Based Macro-Cell Generator / J. Fragoso, F. Moraes, R. Reis 133

Modular Exponentiation on Fine-Grained FPGA / A. Tiountchik, E. Trichina 139

Net by Net Routing with a New Path Search Algorithm / M. Johann, R. Reis 144

Digital Circuit Design Based on the Resonant-Tunneling-Hetero-Junction-Bipolar-Transistor / P. Glosekotter, C. Pacha, K. Goser, G. Wirth, W. Prost, U. Auer, M. Agethen, P. Velling, F. Tegude 150

Session 7 System Level Design

On the Choice of Models of Computation for Writing Executable Specifications of System Level Designs / I. Jeukens, M. Strum 159

Functional Redundancy for Dynamic Exploitation of Performance-Energy Consumption Trade-Offs / V. Ferreira, H. Yasuura 165

Modeling an E1/TU12 Mapper for SDH Systems / R. Silveira, W. Van Noije 171

JPEG Decoding in an Electronic Voting Machine / R. Jacobi, F. Trindade, J. de Carvalho, R. Cantanhede 177

Session 8 Industrial Applications/Applications of FPGAs

An FPGA Implementation of the ATM Layer / J. de Lima, E. Melchier, H. da Silva 185

Prototyping a Pager-Like Device Using FPGAs: Design of an Object Finder / G. Vasquez, W. Van Noije, S. Barbin 191

Jet Determination in Liquid Argon Calorimeters Using a Heavily Interconnected System of Field Programmable Gate Arrays / B. Dulny, J. Fent, W. Haberer, C. Kiesling, A. Osthoff 197

Prototyping of a Biologically-Plausible Vision System for Robotic Applications / R. Zapata, P. Lepinay, L. Torres, J. Droulez, V. Creuze 202

Session 9 Digital Design

Hybrid Latch Flip-Flop with Improved Power Efficiency / N. Nedovic, V. Oklobdzija 211

SisECO: Design of an Echo-Canceling IC for Base Band Modens / L. Agostini, G. Stemmer, A. Prado, R. Pacheco, T. Campos, S. Bampi, R. Reis 216

Modeling of Short Circuit Power Consumption Using Timing-Only Logic Cell Macromodels / E. da Costa, F. Cortes, R. Cardoso, L. Carro, S. Bampi 222

The Use of Extended TSPC CMOS Structures to Build Circuits with Doubled Input/Output Data Throughput / J. Navarro, W. Van Noije 228

Session 10 Fault Tolerant Design

Evaluation of Soft Error Tolerance Technique Based on Time and/or Space Redundancy / L. Anghel, D. Alexandrescu, M. Nicolaidis 237

Optimized Generation of VHDL Mutants for Injection of Transition Errors / R. Leveugle, K. Hadjiat 243

Recent Improvements on the Specification of Transient-Fault Tolerant VHDL Descriptions: A Case-Study for Area Overhead Analysis / F. Vargas, A. Amory 249

Designing a Radiation Hardened 8051-Like Micro-Controller / F. de Lima, E. Cota, L. Carro, M. Lubaszewski, R. Reis, R. Velazco, S. Rezgui 255

Session 11 Formal Methods and H/S Co-Design

JADE: An Embedded Systems Specification, Code Generation and Optimization Tool / C. Pereira, R. Duarte, C. Coelho, Jr., D. da Silva, Jr., A. Fernandes, L. Ambrosio, L. Canaan 263

An ACL2 Model of VHDL for Symbolic Simulation and Formal Verification / V. Rodrigues, D. Borrione, P. Georgelin 269

A New Approach to Solving the Hardware-Software Partitioning Problem in Embedded System Design / D. Engels, S. Devadas 275

Design of a Classification System for Rectangular Shapes Using a Co-Design Environment / R. Molz, P. Engel, F. Moraes, L. Torres, M. Robert 281

Session 12 Analog and Mixed-Signal Design

Fault Models and Compact Test Vectors for MOS OpAmp Circuits / J. Calvano, V. Alves, M. Lubaszewski, A. Mesquita 289

Toward Analog Circuit Synthesis: A Global Methodology Based upon Design of Experiments / Y. Deval, J-B. Begueret, J. Tomas, P. Fouillat 295

A JAVA-Based Mixed-Signal Design Environment / J. Mades, T. Schneider, M. Glesner, A. Windisch, W. Ecker 301

Testing Mixed-Signal Cores / G. Huertas, D. Vazquez, E. Peralias, A. Rueda, J. Huertas 307

Session 13 Physical Modeling

What is the Appropriate Model for Crosstalk Control? / L. Scheffer 315

Efficient vMOS Realization of Threshold Voters for Self-Purging Redundancy / J. Quintana, M. Avedillo, E. Rodriguez-Villegas, A. Rueda 321

LASCA

Interconnect Parasitic Extraction Tool for Deep-Submicron IC Design / F. Ferreira, F. Moraes, R. Reis 327

An Integrated Circuit for the in situ Characterization of CMOS Post-Process Micromachining / B. Warneke, K. Pister 333

Session 14 Reconfigurable Hardware

An Application-Tailored Dynamically Reconfigurable Hardware Architecture for Digital Baseband Processing / J. Becker, T. Pionteck, M. Glesner 341

Exploiting FPGA-Based Architectures and Design Tools for Problems of Reconfigurable Computations / I. Skliarova, A. Ferrari 347

Synthesis of Control Circuits with Dynamically Modifiable Behavior on the Basis of Statically Reconfigurable FPGAs / V. Sklyarov 353

Implementation of Cryptographic Applications on the Reconfigurable FPGA Coprocessor microEnable / H. Singpiel, H. Simmler, A. Kugel, R. Manner, A. Vieira, F. Galvez-Durand, J. Alcantara, V. Alves 359

Session 15 Low-Power, Low-Voltage

Limits to Voltage Scaling from the Low Power Perspective / A. Forestier, M. Stan 365

Adaptive Partial Businvert Encoding for Power-Efficient Data Transfer over Wide System Buses / C. Kretzschmar, R. Siegmund, D. Muller 371

Energy-Efficient Register Access / J. Tseng, K. Asanovic 377

Session 16 Embedded Systems

Design and Simulation of Heterogenous Embedded Systems / K. Mueller-Glaser, S. Schmerler, W. Stork, A. Wagner, J. Drescher, M. Kuehl 385

A Comparison of OO and Reactive Based Specifications on the Design of Embedded Systems / S. Ito, J. Mattos, L. Carro, S. Toscani 391

A Comparison of Microcontrollers Targeted to FPGA-Based Embedded Applications / S. Ito, L. Carro 397.

Notes:

Includes bibliographical references and index.

ISBN:

076950843X

9780769508436

OCLC:

45135146

Access Restriction:

Restricted for use by site license.