IEEE International Conference on Application-Specific Systems, Architectures and Processors. proceedings, July 10-12, 2000 ; Boston, Massachusetts / edited by Earl E. Swartzlander, jr., Graham A. Jullien, Michael J. Schulte ; sponsored by IEEE Computer Society.

Format:

Book

Conference/Event

Contributor:

Swartzlander, Earl E., Jr., 1945-

Jullien, Graham.

Schulte, Michael Joseph, 1967-

IEEE Xplore (Online service)

IEEE Computer Society.

Conference Name:

International Conference on Application-Specific Systems, Architectures, and Processors (12th : 2000 : Boston, Mass.)

Language:

English

Subjects (All):

Array processors--Congresses.

Array processors.

Signal processing--Digital techniques--Congresses.

Signal processing.

Signal processing--Digital techniques.

Application-specific integrated circuits--Congresses.

Application-specific integrated circuits.

Genre:

Conference papers and proceedings.

Physical Description:

xiv, 360 pages : illustrations

Other Title:

Proceedings 2000, the International Conference on Application Specific Systems, Architectures, and Processors

Proceedings 2000, Application-Specific Systems, Architectures, and Processors

Application Specific Systems, Architectures, and Processors

ASAP 2000

Application-Specific Systems, Architectures, and Processors, 2000, proceedings, IEEE International Conference on.

Place of Publication:

Los Alamitos, Calif. : IEEE Computer Society, [2000]

System Details:

Mode of access: World Wide Web.

text file

Contents:

High-Performance Front-End Embedded Signal Processors for Adaptive Sensor Arrays / W. Song xiii

Video and Multimedia Processors / Jurgen Teich

Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures / R. Lee 3

Architecture of an Image Rendering Co-Processor for MPEG-4 Systems / M. Berekovic, P. Pirsch, T. Selinger, K.-I. Wels, C. Miro, A. Lafage, C. Heer, G. Ghigo 15

A Multiplication-Free Parallel Architecture for Affine Transformation / W. Badawy, M. Bayoumi 25

A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications / M. Dal Poz, J. Aedo Cobo, W. Van Noije, M. Zuffo 35

Reconfigurable Computing / Doran Wilde

Formal Verification for Microprocessors with Extendable Instruction Set / S. Sawitzki, R. Spallek, J. Schonherr, B. Straube 47

Compiling Image Processing Applications to Reconfigurable Hardware / R. Rinker, J. Hammes, W. Najjar, W. Bohm, B. Draper 56

Integration of High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality / H. Blume, H.-M. Bluthgen, C. Henning, P. Osterloh 66

Modeling and Synthesis / Shuvra Bhattacharyya

High Level Modeling for Parallel Executions of Nested Loop Algorithms / E. Deprettere, E. Rijpkema, P. Lieverse, B. Kienhuis 79

Minimal Complexity Hierarchical Loop Representations of SFG Processors for Optimal High Level Synthesis / A. Stone, E. Manolakos 92

High Level Synthesis for Peak Power Minimization Using ILP / W.-T. Shiue 103

High-Level Synthesis of Nonprogrammable Hardware Accelerators / R. Schreiber, S. Aditya, B. Ramakrishna Rau, V. Kathail, S. Mahlke, S. Abraham, G. Snider 113

Cryptography / Ruby Lee

Implementing 1,024-bit RSA Exponentiation on a 32-bit Processor Core / B. Phillips, N. Burgess 127

Bit Permutation Instructions for Accelerating Software Cryptography / Z. Shi, R. Lee 138

Performance-Scalable Array Architectures for Modular Multiplication / W. Freking, K. Parhi 149

Digital Signal Processing / Joseph Cavallaro

A 108 Gbps, 1.5 GHz 1D-DCT Architecture / A. Shams, M. Bayoumi 163

Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station Receivers / S. Rajagopal, S. Bhashyam, J. Cavallaro, B. Aazhang 173

A Vector Multiprocessor for Real-Time Multi-User Detection in Spread-Spectrum Communication / N. Manjikian 185

A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-[mu]m CMOS Viterbi Decoder / V. Gierenz, O. Weiss, T. Noll, I. Carew, J. Ashley, R. Karabed 195

Arithmetic / Magdy Bayoumi

A Booth Multiplier Accepting Both a Redundant or a Non-Redundant Input with No Additional Delay / M. Daumas, D. Matula 205

A Hardware Algorithm for Variable-Precision Logarithm / J. Hormigo, J. Villalba, M. Schulte 215

Block-Update Parallel Processing QRD-RLS Algorithm for Throughput Improvement with Low Power Consumption / L. Gao, K. Parhi 225

A 16-bit x 16-bit MAC Design Using Fast 5:2 Compressors / O. Kwon, K. Nowka, E. Swartzlander 235

Multiprocessor Systems / Ed Deprettere

Control for High-Speed PE Arrays / M. Herbordt, J. Cravy, H. Zhang, C. Lin, H. Rao 247

Explicit SIMD Programming for Asynchronous Applications / A. Di Blas, R. Hughey 258

Quadratic Control Signals in Linear Systolic Arrays / S. Bowden, D. Wilde, S. Rajopadhye 268

Contention-Conscious Transaction Ordering in Embedded Multiprocessors / M. Khandelia, S. Bhattacharyya 276

Application-Specific Architectures / Neil Burgess

Architecture for Wavelet Packet Transform with Best Tree Searching / M. Trenas, J. Lopez, M. Sanchez, F. Arguello, E. Zapata 289

Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter / M. Bednara, O. Beyer, J. Teich, R. Wanka 299

A Programmable Processor for Approximate String Matching with High Throughput Rate / H.-M. Bluthgen, T. Noll 309

Design Methodology / Elias Manolakos

A New Algorithm for the Elimination of Common Subexpressions in Hardware Implementation of Digital Filters by Using Genetic Programming / H. Safiri, M. Ahmadi, G. Jullien, W. Miller 319

A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors / R. Govindarajan, E. Altman, G. Gao 329

Partitioning Conditional Data Flow Graphs for Embedded System Design / M. Auguin, L. Bianco, L. Capella, E. Gresset 339

Generation of Scheduling Functions Supporting LSGP-Partitioning / D. Fimmel 349.

Notes:

"IEEE Computer Society order number PR00716"--T.p. verso.

"IEEE order plan catalog number 97TB100177"--Cover p. 4.

Includes bibliographical references and author index.

ISBN:

0769507166

9780769507163

0769507182

9780769507187

OCLC:

44788873

Access Restriction:

Restricted for use by site license.