Proceedings, Sixth International Symposium on High-Performance Computer Architecture, HPCA-6. January 8-12, 2000, Toulouse, France / sponsored by IEEE Computer Society Technical Committee on Computer Architecture, with the support of Région Midi-Pyrénees ... [and others].

Format:

Book

Conference/Event

Contributor:

IEEE Xplore (Online service)

IEEE Computer Society. Technical Committee on Computer Architecture.

Midi-Pyrénées (France). Conseil régional.

Conference Name:

International Symposium on High-Performance Computer Architecture (6th : 2000 : Toulouse, France)

Language:

English

Subjects (All):

Computer architecture--Congresses.

Computer architecture.

High performance computing--Congresses.

High performance computing.

Genre:

Conference papers and proceedings.

Physical Description:

xiii, 420 pages : illustrations

Other Title:

HPCA

Sixth International Symposium on High-Performance Computer Architecture

High-performance computer architecture

HPCA-6

High-Performance Computer Architecture, 2000, HPCA-6, proceedings, Sixth International Symposium on.

Place of Publication:

Los Alamitos, Calif. : IEEE Computer Society, [1999]

System Details:

Mode of access: World Wide Web.

text file

Contents:

Relaxing Constraints: Thoughts on the Evolution of Computer Architecture / Joel Emer, Compaq Computer Corporation

Session 1 System Architecture Tradeoffs

Impact of Chip-Level Integration on Performance of OLTP Workloads / L. Barroso, K. Gharachorloo, A. Nowatzyk, B. Verghese 3

Toward a Cost-Effective DSM Organization That Exploits Processor-Memory Integration / J. Torrellas, L. Yang, A-T. Nguyen 15

Impact of Heterogeneity on DSM Performance / R. Figueiredo, J. Fortes 26

Session 2a Memory and Cache

Design of a Parallel Vector Access Unit for SDRAM Memory Systems / B. Mathew, S. McKee, J. Carter, A. Davis 39

Modified LRU Policies for Improving Second-Level Cache Behavior / W. Wong, J-L. Baer 49

eXtended Block Cache / S. Jourdan, L. Rappoport, Y. Almog, M. Erez, A. Yoaz, R. Ronen 61

Session 2b Networks

Flit-Reservation Flow Control / L-S. Peh, W. Dally 73

Performance Evaluation of Dynamic Reconfiguration in High-Speed Local Area Networks / R. Casado, A. Bermudez, F. Quiles, J. Sanchez, J. Duato 85

Investigating QoS Support for Traffic Mixes with the MediaWorm Router / K. Yum, A. Vaidya, C. Das, A. Sivasubramaniam 97

Session 3a Multithreading and Microarchitecture

Quantifying the SMT Layout Overhead

Does SMT Pull Its Weight? / J. Burns, J-L. Gaudiot 109

Software-Controlled Multithreading Using Informing Memory Operations / T. Mowry, S. Ramkissoon 121

Dynamic Cluster Assignment Mechanisms / R. Canal, J. Parcerisa, A. Gonzalez 133

Session 3b Shared Memory

High-Throughput Coherence Controllers / A. Nanda, A-T. Nguyen, M. Michael, D. Joseph 145

Coherence Communication Prediction in Shared-Memory Multiprocessors / S. Kaxiras, C. Young 156

Improving the Throughput of Synchronization by Insertion of Delays / R. Rajwar, A. Kagi, J. Goodman 168

Panel Session I

Impact of Interconnect on Computer Architecture / Bill Dally

2K Papers on Caches by Y2K: Do We Need More? / Jean-Loup Baer

Session 4 Software Techniques

On the Performance of Hand vs. Automatically Optimized Numerical Codes / M. Jimenez, J. Llaberia, A. Fernandez 183

Cache-Efficient Matrix Transposition / S. Chatterjee, S. Sen 195

A Prefetching Technique for Irregular Accesses to Linked Data Structures / M. Karlsson, F. Dahlgren, P. Stenstrom 206

Reducing Code Size with Run-Time Decompression / C. Lefurgy, E. Piccininni, T. Mudge 218

Session 5a Prediction I

Decoupled Value Prediction on Trace Processors / S-J. Lee, Y. Wang, P-C. Yew 231

Branch Transition Rate: A New Metric for Improved Branch Classification Analysis / M. Haungs, P. Sallee, M. Farrens 241

Combining Static and Dynamic Branch Prediction to Reduce Destructive Aliasing / H. Patil, J. Emer 251

Session 5b Parallel Systems

The Effect of Network Total Order, Broadcast, and Remote-Write Capability on Network-Based Shared Memory Computing / R. Stets, S. Dwarkadas, L. Kontothanassis, U. Rencuzogullari, M. Scott 265

PowerMANNA: A Parallel Architecture Based on the PowerPC MPC620 / P. Behr, S. Pletner, A. Sodan 277

A DSM Architecture for a Parallel Computer Cenju-4 / T. Hosomi, Y. Kanoh, M. Nakamura, T. Hirose 287

Session 6a Prediction II

Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors / A. Moshovos, G. Sohi 301

A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks / H. Neefs, H. Vandierendonck, K. De Bosschere 313

Trace Cache Redundancy: Red & Blue Traces / A. Ramirez, J. Larriba-Pey, M. Valero 325

Session 6b Parallel Systems Performance

Evaluation of Active Disks for Decision Support Databases / M. Uysal, A. Acharya, J. Saltz 337

Investigating the Performance of Two Programming Models for Clusters of SMP PCs / F. Cappello, O. Richard, D. Etiemble 349

Performance Analysis and Visualization of Parallel Systems Using SimOS and Rivet: A Case Study / R. Bosch, C. Stolte, G. Stoll, M. Rosenblum, P. Hanrahan 360

Work-in-progress / Sally McKee

Networking at Home

Directions in Connected Computing for the Consumer / Kevin Kahn

Session 7 Novel Architecture Issues

Register Organization for Media Processing / S. Rixner, W. Dally, B. Khailany, P. Mattson, U. Kapasi, J. Owens 375

Architectural Issues in Java Runtime Systems / R. Radhakrishnan, N. Vijaykrishnan, L. John, A. Sivasubramaniam 387

The Best Distribution for a Parallel OpenGL 3D Engine with Texture Caches / A. Vartanian, J-L. Bechennec, N. Drach-Temam 399

Cache Memory Design for Network Processors / T-C. Chiueh, P. Pradhan 409

Workshop Overviews

4th Workshop on Communication, Architecture, and Applications for Network-Based Parallel Computing (CANPC)

4th Workshop on Interaction between Compilers and Computer Architectures (INTERACT)

4th Workshop on Multithreaded Execution, Architecture, and Compilation (MTEAC)

2nd Workshop on Parallel Computing for Irregular Applications (WPCIA2)

3rd Workshop on Computer Architecture Evaluation Using Commercial Workloads (CAECW)

Tutorial on Performance Modeling Using Hardware Counters.

Notes:

"IEEE Computer Society Order Number PR00550"--T.p. verso.

"IEEE Order Plan Catalog Number PR00550"--T.p. verso.

Includes bibliographical references and index.

ISBN:

0769505503

9780769505503

076950552X

9780769505527

OCLC:

43462649

Access Restriction:

Restricted for use by site license.