VLSI Design 2000. Thirteenth International Conference on VLSI Design : 3-7 January 2000, Science City, Calcutta, India / [sponsored by VLSI Society of India (VSI), DOE, Government of India ; in cooperation with Association for Computing Machinery, IEEE Circuits and Systems Society ... and others].

Format:

Book

Conference/Event

Contributor:

IEEE Xplore (Online service)

VLSI Society of India.

India. Department of Electronics.

IEEE Circuits and Systems Society.

Conference Name:

International Conference on VLSI Design (13th : 2000 : Science City, Calcutta, India)

Language:

English

Subjects (All):

Integrated circuits--Very large scale integration--Design and construction--Congresses.

Integrated circuits.

Integrated circuits--Very large scale integration--Design and construction.

Signal processing--Digital techniques--Congresses.

Signal processing.

Signal processing--Digital techniques.

Electronic digital computers--Circuits--Congresses.

Electronic digital computers.

Electronic digital computers--Circuits.

Genre:

Conference papers and proceedings.

Physical Description:

xxxiv, 588 pages : illustrations

Other Title:

Wireless and digital imaging in the millennium

Proceedings of the 13th International Conference on VLSI Design

Place of Publication:

Los Alamitos, Calif. : IEEE Computer Society Press, [2000]

System Details:

Mode of access: World Wide Web.

text file

Contents:

T1 Power Reduction Techniques for Portable DSP Applications / M. Mehendale, S.D. Sherlekar 3

(a) Theory and Applications of Cellular Automata for VLSI Design and Testing / P. Pal Chaudhuri, D. Roy Chowdhury, K. Paul, B. Sikdar 4

(b) Test Techniques and Trade-offs for Embedded Cores and Systems / R. Parekhji 5

(a) Computer-aided Design of RF Communication Systems: Techniques and Challenges / L. Nagel, J. Roychowdhury 6

(b) Analog Circuits for Wireless Communications / R. Harjani 7

T4 New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits / M. Breuer, S. Gupta 8

T5 Core Based ASIC Design / F. Higgins, S. Bhawmik 10

(a) Partition, Packing and Clock Distribution

A New Paradigm of Physical Design / Y. Kajitani, A. Takahashi, K. R. Azegami, S. Nakatake 11

(b) Low Power VLSI Signal Processing / K. Roy, K. Muhammad 12

Keynote Address: Computing and Communication in the New Millennium / Avtar Saini 15

Embedded Tutorial: Wire Technology Drivers for the New Millennium / A. R. Gupta

Embedded Tutorial: Semiconductors for Communications: Key Platform Technologies / M. V. Atre

Invited Talk: System-on-Chips/IP Technologies: Opportunities and Challenges / T. J. Chakraborty

Invited Talk: SONET IC Design: Overview and Case Studies / K. Mandal

Invited Talk: Wireless Market Evolution / M. Prakash

EDA

The Next Generation / Ajoy Bose 19

IP Reuse in System on a Chip Design / Raul Camposano 20

Papers

Session 1A Low Power Design

Invited Talk: Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs / L. Wei, K. Roy, V.K. De 24

Low Power Realization of Residue Number System Based FIR filters / M.N. Mahesh, M. Mehendale 30

An Assertion Based Technique for Transistor Level Dynamic Power Estimation / S. Savithri, R. Venkatesan, S. Bhaskar 34

Relating Data Characteristics to Transition Activity in High-level Static CMOS Design / R. Henning, C. Chakrabarti 38

A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25[mu]m SOI Technology / R.V. Joshi, W. Hwang, S. Wilson, G. Shahidi, C.T. Chuang 44

Embedded Tutorial: Energy Aware Software / A. Sinha, A.P. Chandrakasan 50

Session 1B Formal Verification

Embedded Tutorial: Performance and Functional Verification of Microprocessors / P. Bose, J.A. Abraham 58

Automatic Component Matching Using Forced Simulation / P.S. Roop, A. Sowmya, S. Ramesh 64

Status Condition Analysis During Data Path Verification of Sequential Circuits / D. Sarkar 70

Modelling VHDL in Multiclock Esterel / B. Rajan, R.K. Shyamasundar 76

Formal Verification of Synthesized Mixed Signal Designs Using *BMDs / A. Ghosh, R. Vemuri 84

Session 1C Embedded Systems I

Embedded Tutorial: Interface Synthesis: Issues and Approaches / A. Rajawat, M. Balakrishnan, A. Kumar 92

Processor Evaluation in an Embedded Systems Design Environment / T.V.K. Gupta, P. Sharma, M. Balakrishnan, S. Malik 98

Combining Background Memory Management and Regular Array Co-partitioning, Illustrated on a Full Motion Estimation Kernel / R. Schaffer, R. Merker, F. Catthoor 104

Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming / A. Shrivastava, M. Kumar, S. Kapoor, S. Kumar, M. Balakrishnan 110

COWLS: Hardware-Software Co-synthesis of Distributed Wireless Low-power Embedded Client-server Systems / R.P. Dick, N.K. Jha 114

Session 2A Digital Imaging I

Invited Talk: Challenges of Merging Digital Imaging and Wireless Communication / W. Metz, T. Acharya 122

Design of an ASIC for Straight Line Detection in an Image / A.K. Majumdar, N. Patel 128

Digital Imaging with Wireless Data Services / S. Sarkar 134

GF(2[superscript p]) CA Based Vector Quantization For Fast Encoding of Still Images / K. Paul, S.P. Chaudhuri, R. Ghosal, B. Sikdar, D.R. Choudhury 140

Scalable Pipelined Micro-Architecture for Wavelet Transform / K. Paul, D.R. Chowdhury, P.P. Chaudhuri 144

Session 2B Signal Integrity I

Invited Talk: Interconnect Statistical Modeling: Structures and Measurement Methodologies / A. Doganis 150

Invited Talk: Design and Analysis of Power Distribution Networks with Accurate RLC Models / R. Chaudhry, R. Panda, D. Blauw, T. Edwards 151

A Methodology for the Placement and Optimization of Decoupling Capacitators for Gigahertz Systems / J. Choi, S. Chun, N. Na, M. Swaminathan, L. Smith 156

Inductive Noise Reduction at the Architectural Level / M.D. Pant, P. Pant, D.S. Wills, V. Tiwari 162

Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits / S. Zhao, K. Roy 168

Session 2C Testing I

Embedded Tutorial: Manufacturing and Test Considerations in System-on-chip Designs / M. d'Abreu 176

Cost Trade-offs in System On Chip Designs / J. Khare, H.T. Heineken, M. d'Abreu 178

Manufacturability and Testability Oriented Synthesis / S.A. Shaikh, J. Khare, H.T. Heineken 185

Maximizing Wafer Productivity through Layout Optimizations / C. Ouyang, H.T. Heineken, J. Khare, S. Shaikh, M. d'Abreu 192

Hierarchical Test Generation for Systems on a Chip / R.S. Tupuri, J.A. Abraham, D.G. Saab 198

Session 3A High-level Synthesis

A Genetic Algorithm for the Synthesis of Structured Data Paths / C. Mandal, R.M. Zimmer 206

A Technique for Dynamic High-level Exploration During Behavioral-partitioning for Multi-device Architectures / S. Govindarajan, V. Srinivasan, P. Lakshmikanthan, R. Vemuri 212

High-level Synthesis with Variable-latency Components / V. Raghunathan, S. Ravi, G. Lakshminarayana 220

CREAM: Combined Register and Module Assignment with Floorplanning for Low Power Datapath Synthesis / V.K. Srikantam, N. Ranganathan, S. Srinivasan 228

Design Partitioning on Single-chip Emulation Systems / A. Ejnioui, N. Ranganathan 234

Delay-constrained Area Recovery via Layout-driven Buffer Optimization / R. Murgai 240

Session 3B Layout & Floorplanning

Routing on Switch Matrix Multi-FPGA Systems / A. Ejnioui, N. Ranganathan 248

A Transistor Level Placement Tool for Custom Cell Generation / R.K. Dash, T. Pramod, V. Vasudevan, M. Ramakrishna 254

On the Transistor Sizing Problem / A. Das 258

Evaluation of Various Routing Architectures for Multi-FPGA Boards / S.C. Jain, S. Kumar, A. Kumar 262

A Fast Graph-based Alternative Wiring Scheme for Boolean Networks / Y-L. Wu, W. Long, H. Fan 268

Topological Routing amidst Polygonal Obstacles / S. Bhunia, S. Majumder, A. Sircar, S. Sur-Kolay, B.B. Bhattacharya 274

A Tight Area Upper Bound for Slicing Floorplans / H.P. Peixoto, M.F. Jacome, A. Royo 280

Session 3C Testing II

Embedded Tutorial: A New Definition and a New Class of Sequential Circuits with Combinational Test Generation Complexity / H. Fujiwara 288

Test Transformation to Improve Compaction by Statistical Encoding / H. Ichihara, K. Kinoshita, I. Pomeranz, S.M. Reddy 294

Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency / H. Wada, T. Masuzawa, K.K. Saluja, H. Fujiwara 300

Choice of Tests for Logic Verification and Equivalence Checking and the Use of Fault Simulation / V.D. Agrawal 306

Automatic Validation Test Generation Using Extracted Control Models / R. Sumners, J. Bhadra, J. Abraham 312

DSP

The Real Time Technology for the New Millennium / John Scarisbrick 321

Surviving the SOC Revolution: The Platform Approach to SOC Design / Grant Martin 325

Session 4A Digital Imaging II / A.K. Majumdar, T. Acharya

A Fast Algorithm for Computing the Euler Number of an Image and its VLSI Implementation / S. Dey, B.B. Bhattacharya, M.K. Kundu, T. Acharya 330

Optimization of the One-dimensional Full Search Algorithm and Implementation Using an EPLD / R.T.N. Rajaram, V. Vasudevan 336

A Single-chip Programmable Digital CMOS Imager with Enhanced Low-light Detection Capability / B. Pain, G. Yang, M. Ortiz, K. McCarty, B. Hancock, J. Heynssens, T. Cunningham, C. Wrigley, C. Ho 342

Session 4B Design

Architecture and Implementation of a High-Definition Video Co-processor for Digital Television Applications / S. Dutta, D. Singh, E. Abu-Ghoush, V. Mehra 350

Specification and Design of a Quasi-delay-insensitive Java Card Microprocessor / F-C. Cheng, C-R. Wang 356

Invited Talk: Trends in Communication Technology and Its Impact on Semiconductor / S. Das 362

Session 4C Signal Integrity II

Invited Talk: Capturing the Effect of Crosstalk on Delay / S.S. Sapatnekar 364

A Practical Approach to Crosstalk Noise Verification of Static CMOS Designs / N.S. Nagaraj, F. Cano, D. Young, D. Vohra, M. Das 370

Inductance Characterization of Small Interconnects Using Test-signal Method / J.T. Shah, M.P. Desai, S. Sanyal 376

Session 5A Testing III

Zero-Aliasing Space Compression Using a Single Periodic Output and its Application to Testing of Embedded Cores / B.B. Bhattacharya, A. Dmitriev, M. Goessel 382

Testing Interconnects in a System Chip / C.P. Ravikumar, S. Chopra 388

On Synchronizing Sequences and Unspecified Values in Output Responses of Synchronous Sequential Circuits / I. Pomeranz, S.M. Reddy 392

Resource-constrained Compaction of Sequential Circuit Test Sets / S.K. Bommu, S.T. Chakradhar, K.B. Doreswamy 398

Testing Flash Memories / M.G. Mohammad, K.K. Saluja, A. Yap 406

A Versatile BIST Technique Combining Test Registers and Accumulators / F. Mayer, A.P. Stroele 412

Session 5B Verification

Dataflow Analysis for Resource Contention and Register Leakage Properties / S.K. Roy, H. Iwashita, T. Nakata 418

Retargetable Functional Simulator Using High Level Processor Models / S. Chandra, R. Moona 424

State-machine Based Logic Simulation Using Three Logic Values / P.M. Maurer, W.J. Schilp 430

Hierarchical Error Diagnosis Targeting RTL Circuits / V. Boppana, I. Ghosh, R. Mukherjee, J. Jain, M. Fujita 436

Fast Error Diagnosis for Combinational Verification / A. Gupta, P. Ashar 442

Verification of a Combinational Loop Based Arbitration Scheme in a System-on-chip Integration Architecture / Y. Xia, P. Ashar 449

Session 5C Embedded Systems II

Efficient Implementation of ADPCM Codec / A. Sharma, C.P. Ravikumar 456

Simultaneous Module Selection and Scheduling for Power-constrained Testing of Core Based Systems / C.P. Ravikumar, G. Chandra, A. Verma 462

A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores / K. Madathil, J.C. Rao, S. Chander, A. Menon, A.K Gautam, A.M. Brahme, H. Udayakumar 468

Session 6A Analog / Mixed-signal Circuits

Embedded Tutorial: SOI Digital Circuits: Design Issues / R. Puri, C.T. Chuang 474

Jitter Estimation Methodology for Clock Chips / S.K. Maheshwari, G.S. Visweswaran, R.S. Krishanan 480

A 3.3V Compatible 2.5V TTL-to-CMOS Bidirectional I/O Buffer / S.K. Maheshwari, G.S. Visweswaran 484

Silicon Heterostructure Devices for RF Wireless Communication / B. Senapati, C.K. Maiti, N.B. Chakrabarti 488

Design of OTA Based Field Programmable Analog Array / B. Ray, P.P. Chaudhuri, P.K. Nandi 492

Convergence Issues in Resonant Tunneling Diode Circuit Simulation 499

Session 6B Synthesis and Timing Analysis

Spectral Theory of Disjunctive Decomposition for Balanced Boolean Functions / B.J. Falkowski, S. Kannurao 506

Synthesizable RAM

Alternative to Low Configuration Compiler Memory for Die Area Reduction / B. Suresh, B. Chaterjee, R. Harinath 512

Timing Analysis with Implicitly Specified False Paths / E. Goldberg, A. Saldanha 518

Clock Selection for Performance Optimization of Control-flow Intensive Behaviors / K.S. Khouri, N.K. Jha 523

Performance Analysis of Systems with Multi-channel Communication Architectures / K. Lahiri, A. Raghunathan, S. Dey 530

An ASIC for Cellular Automata Based Message Authentication / P. Dasgupta, S. Chattopadhyay, I. Sengupta 538

Session 6C Testing IV

Cellular Automata Based Deterministic Test Sequence Generator for Sequential Circuits / P. Dasgupta, S. Chattopadhyay, I. Sengupta 544

An Efficient Hierarchical Fault Isolation Technique for Mixed-signal Boards / S. Cherubal, A. Chatterjee 550

Theory and Application of GF(2[superscript p]) Cellular Automata as On-chip Test Pattern Generator / B.K. Sikdar, K. Paul, G.P. Biswas, V. Boppana, C. Yang, S. Mukherjee, P.P. Chaudhuri 556

Application of GF(2[superscript p]) CA in Burst Error Correcting Codes / K. Paul, D.R. Chowdhury 562

Built-in Self-test in Mixed-signal ICs: A DTMF Macrocell / G. Huertas, D. Vazquez, A. Rueda, J.L. Huertas 568

A Mixed-signal BIST Scheme with Time-division Multiplexing (TDM) Comparator and Counters / J. Roh, J.A. Abraham 572

VLSI Design 1999 Paper (late arrival)

Design of Synchronous Action Systems / J. Plosila, T. Seceleanu 578

VLSI Design 2001 Call for Papers 587.

Notes:

Includes bibliographical references and author index.

"IEEE Computer Society Order Number PR00487"--T.p. verso.

ISBN:

0769504876

9780769504872

0769504892

9780769504896

OCLC:

43400941

Access Restriction:

Restricted for use by site license.