Proceedings. International Workshop on Memory Technology, Design, and Testing / edited by F. Lombardi, R. Rajsuman, and T. Wik ; sponsored by IEEE Computer Society, IEEE Computer Society Technical Committee on Test Technology, IEEE Computer Society Technical Committee on VLSI ; in cooperation with IEEE Solid State Circuits Council.

Format:

Book

Conference/Event

Contributor:

Lombardi, Fabrizio, 1955-

Rajsuman, Rochit.

Wik, T. (Thomas)

IEEE Xplore (Online service)

IEEE Computer Society. Test Technology Technical Committee.

IEEE Computer Society. Technical Committee on VLSI.

Conference Name:

IEEE International Workshop on Memory Technology, Design, and Testing (1997 : San Jose, Calif.)

Language:

English

Subjects (All):

Semiconductor storage devices--Testing--Congresses.

Semiconductor storage devices.

Random access memory--Congresses.

Random access memory.

Semiconductor storage devices--Testing.

Genre:

Conference papers and proceedings.

Physical Description:

ix, 103 pages : illustrations

Other Title:

Records of the IEEE International Workshop on Memory Technology, Design and Testing

Memory Technology, Design and Testing

MTDT'97

Memory Technology, Design and Testing, 1997, proceedings, International Workshop on.

Place of Publication:

Los Alamitos, Calif. : IEEE Computer Society Press, [1997]

System Details:

Mode of access: World Wide Web.

text file

Contents:

Matching memory to the power of personal computers / R. Foss

A low-cost, high performance three-dimensional memory module technology / A. Glaser ... [et al.]

High speed circuit techniques in a 150MHz 64M SDRAM / V. Lines ... [et al.]

An analysis of (linked) addressed decoder faults / A. van de Goor, G. Gaydadjiev

SRAM yield estimation in the early stage of the design cycle / V. Kim, T. Chen

False write through and un-restored write electrical level fault models for SRAMs / R. Adams, E. Cooley

A defect-tolerant DRAM employing a hierarchical redundancy scheme, built-in self-test and self-reconfiguration / D. Niggemeyer, J. Otterstedt, M. Redeker

Formal verification of memory arrays using symbolic trajectory evaluation / M. Pandey, R. Bryant

A product development flow with metrics for memory designs / S. Hegde, I. Pal, K. Rao

A low-power high storage capacity structure for GaAs MESFET ROM / R. Kanan ... [et al.]

Use of selective precharge for low-power on the match lines of content-addressable memories / C. Zukowski, S. Wang

An open notation for memory tests / A. Offerman, A. van de Goor

Testing memory modules in SRAM-based configurable FPGAs / W. Huang ... [et al.]

Memory array testing through a scannable configuration / S. Yano, N. Ishiura

A high-speed parallel sensing scheme for multi-level non-volatile memories / C. Calligaro ... [et al.].

Notes:

"August 11-12, 1997, San Jose, California"--Cover.

"IEEE Order Plan Catalog Number 95TB100159"--T.p. verso.

"IEEE Computer Society Order Number PR08099"--T.p. verso.

Includes bibliographical references and index.

ISBN:

0818680997

9780818680991

0818681004

9780818681004

0818681012

9780818681011

OCLC:

37597894

Access Restriction:

Restricted for use by site license.