MICRO-36 2003. 36th International Symposium on Microarchitecture : proceedings : 3-5 December, 2003, San Diego, California / sponsored by IEEE TC-MARCH, SIGMICRO.

Format:

Book

Conference/Event

Contributor:

ACM Digital Library.

IEEE Xplore (Online service)

IEEE Computer Society. Technical Committee on Microprogramming and Microarchitecture.

ACM Special Interest Group on Microprogramming.

Conference Name:

Annual International Symposium on Microarchitecture (36th : 2003 : San Diego, Calif.)

Series:

ACM Digital Library (Series)

Language:

English

Subjects (All):

Computer architecture--Congresses.

Computer architecture.

Microprogramming--Congresses.

Microprogramming.

Genre:

Conference papers and proceedings.

Physical Description:

xiv, 436 pages : illustrations

Other Title:

36th International Symposium on Microarchitecture

IEEE/ACM International Symposium on Microarchitecture

Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture.

Microarchitecture, 2003, MICRO-36, proceedings, 36th Annual IEEE/ACM International Symposium on.

Place of Publication:

Los Alamitos, Calif. : IEEE Computer Society, [2003]

System Details:

Mode of access: World Wide Web.

text file

Contents:

Microarchitecture on the MOSFET Diet / Kerry Bernstein 3

Session 1 Voltage Scaling and Transient Faults / Chair: Antonio Gonzalez

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation / D. Ernst, N. S. Kim, S. Das, S. Pant, R. Rao, T. Pham, C. Ziesler, D. Blaauw, T. Austin, K. Flautner, T. Mudge 7

VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power / H. Li, C.-Y. Cher, T. N. Vijaykumar, K. Roy 19

A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor / S. S. Mukherjee, C. Weaver, J. Emer, S. K. Reinhardt, T. Austin 29

Session 2 Cache Design / Chair: Josep Torrellas

TLC: Transmission Line Caches / B. M. Beckmann, D. A. Wood 43

Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures / Z. Chishti, M. D. Powell, T. N. Vijaykumar 55

Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches / S.-H. Yang, B. Falsafi 67

Session 3 Power and Energy Efficient Architectures / Chair: Todd Austin

Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction / R. Kumar, K. I. Farkas, N. P. Jouppi, P. Ranganathan, D. M. Tullsen 81

Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data / C. Isci, M. Martonosi 93

Power-Driven Design of Router Microarchitectures in On-Chip Networks / H. Wang, L.-S. Peh, S. Malik 105

Optimum Power/Performance Pipeline Depth / A. Hartstein, T. R. Puzak 117

Session 4 Application Specific Optimization and Analysis / Chair: Kemal Ebcioglu

Processor Acceleration through Automated Instruction Set Customization / N. Clark, H. Zhong, S. Mahlke 129

The Reconfigurable Streaming Vector Processor (RSVP) / S. Ciricescu, R. Essick, B. Lucas, P. May, K. Moat, J. Norris, M. Schuette, A. Saidi 141

Scaling and Characterizing Database Workloads: Bridging the Gap between Research and Practice / R. Hankins, T. Diep, M. Annavaram, B. Hirano, H. Eri, H. Nueckel, J. P. Shen 151

In Memory of Bob Rau / Michael Schlansker 165

Session 5 Dynamic Optimization Systems / Chair: Ronny Ronen

Generational Cache Management of Code Traces in Dynamic Optimization Systems / K. Hazelwood, M. D. Smith 169

The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System / J. Lu, H. Chen, R. Fu, W.-C. Hsu, B. Othmer, P.-C. Yew, D.-Y. Chen 180

IA-32 Execution Layer: A Two-Phase Dynamic Translator Designed to Support IA-32 Applications on Itanium-Based Systems / L. Baraz, T. Devor, O. Etzion, S. Goldenberg, A. Skaletsky, Y. Wang, Y. Zemach 191

Session 6 Dynamic Program Analysis and Optimization / Chair: John Shen

LLVA: A Low-Level Virtual Instruction Set Architecture / V. Adve, C. Lattner, M. Brukman, A. Shukla, B. Gaeke 205

Comparing Program Phase Detection Techniques / A. S. Dhodapkar, J. E. Smith 217

Using Interaction Costs for Microarchitectural Bottleneck Analysis / B. A. Fields, R. Bodik, M. D. Hill, C. J. Newburn 228

Session 7 Branch, Value and Scheduling Optimizations / Chair: Glenn Reinman

Fast Path-Based Neural Branch Prediction / D. A. Jimenez 243

Hardware Support for Control Transfers in Code Caches / H.-S. Kim, J. E. Smith 253

Exploiting Value Locality in Physical Register Files / S. Balakrishnan, G. S. Sohi 265

Macro-op Scheduling: Relaxing Scheduling Loop Constraints / I. Kim, M. H. Lipasti 277

Session 8 Dataflow, Data Parallel, and Clustered Architectures / Chair: Matt Farrens

WaveScalar / S. Swanson, K. Michelson, A. Schwerin, M. Oskin 291

Universal Mechanisms for Data-Parallel Architectures / K. Sankaralingam, S. W. Keckler, W. R. Mark, D. Burger 303

Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors / E. Gibert, J. Sanchez, A. Gonzalez 315

Instruction Replication for Clustered Microarchitectures / A. Aleta, J. M. Codina, A. Gonzalez, D. Kaeli 326

Session 9 Secure and Network Processors / Chair: T. N. Vijaykumar

Efficient Memory Integrity Verification and Encryption for Secure Processors / G. E. Suh, D. Clarke, B. Gassend, M. van Dijk, S. Devadas 339

Fast Secure Processor for Inhibiting Software Piracy and Tampering / J. Yang, Y. Zhang, L. Gao 351

IPStash: A Power-Efficient Memory Architecture for IP-Lookup / S. Kaxiras, G. Keramidas 361

Design and Implementation of High-Performance Memory Systems for Future Packet Buffers / J. Garcia, J. Corbal, L. Cerda, M. Valero 373

Session 10 Scaling Design / Chair: Mikko Lipasti

Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining / R. D. Barnes, E. M. Nystrom, J. W. Sias, S. J. Patel, N. Navarro, W. W. Hwu 387

Scalable Hardware Memory Disambiguation for High ILP Processors / S. Sethumadhavan, R. Desikan, D. Burger, C. R. Moore, S. W. Keckler 399

Reducing Design Complexity of the Load/Store Queue / I. Park, C. L. Ooi, T. N. Vijaykumar 411

Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors / H. Akkary, R. Rajwar, S. T. Srinivasan 423.

Notes:

"IEEE Computer Society Order Number PR02034"--T.p. verso.

Includes bibliographical references and author index.

ISBN:

076952043X

9780769520438

OCLC:

53928543

Access Restriction:

Restricted for use by site license.