Proceedings. 33rd Annual IEEE/ACM International Symposium on Microarchitecture : MICRO-33 2000 : Monterey, California, USA, 10-13 December 2000 / sponsored by IEEE TC-MARCH, ACM SIGMICRO, with the generous support of Compaq ... [and others].

Format:

Book

Conference/Event

Contributor:

ACM Digital Library.

IEEE Xplore (Online service)

IEEE Computer Society. Technical Committee on Microprogramming and Microarchitecture.

ACM Special Interest Group on Microprogramming.

Conference Name:

Annual International Symposium on Microarchitecture (33rd : 2000 : Monterey, Calif.)

Series:

ACM Digital Library (Series)

Language:

English

Subjects (All):

Computer architecture--Congresses.

Computer architecture.

Microprogramming--Congresses.

Microprogramming.

Genre:

Conference papers and proceedings.

Physical Description:

xiv, 357 pages : illustrations

Other Title:

MICRO-33

33rd Annual IEEE/ACM International Symposium on Microarchitecture

IEEE/ACM International Symposium on Microarchitecture

Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture.

Microarchitecture, 2000, MICRO-33, proceedings, 33rd Annual IEEE/ACM International Symposium on.

Place of Publication:

Los Alamitos, Calif. : IEEE Computer Society, [2000]

System Details:

Mode of access: World Wide Web.

text file

Contents:

A Whole New Ballgame-Supercomputing on Two AA Batteries / David Baker 3

Breathing Life into a Paper Tiger / Darrell Boggs 5

Defect Tolerant Molecular Electronics: Algorithms, Architectures, and Atoms / Phil Keukes 7

Memory Hierarchy I / Ronny Ronen

Eager Writeback

A Technique for Improving Bandwidth Utilization / H.-H. S. Lee, G. S. Tyson, M. K. Farrens 11

Silent Stores for Free / K. M. Lepak, M. H. Lipasti 22

A Permutation-Based Page Interleaving Scheme to Reduce Row-Buffer Conflicts and Exploit Data Locality / Z. Zhang, Z. Zhu, X. Zhang 32

Predictor-Directed Stream Buffers / T. Sherwood, S. Sair, B. Calder 42

Superscalar Architecture I / Gary Tyson

On Pipelining Dynamic Instruction Scheduling Logic / J. Stark, M. D. Brown, Y. N. Patt 57

The Impact of Delay on the Design of Branch Predictors / D. A. Jimenez, S. W. Keckler, C. Lin 67

Improving BTB Performance in the Presence of DLLs / S. Vlaovic, E. S. Davidson, G. S. Tyson 77

Efficient Checker Processor Design / S. Chatterjee, C. Weaver, T. Austin 87

Compilation / Carol Thompson

An Integrated Approach to Accelerate Data and Predicate Computations in Hyperblocks / A. Eichenberger, W. Meleis, S. Maradani 101

Accurate and Efficient Predicate Analysis with Binary Decision Diagrams / J. W. Sias, W. W. Hwu, D. I. August 112

Modulo Scheduling for a Fully-Distributed Clustered VLIW Architecture / J. Sanchez, A. Gonzalez 124

Accelerator Architecture / Tom Conte

Two-Level Hierarchical Register File Organization for VLIW Processors / J. Zalamea, J. Llosa, E. Ayguade, M. Valero 137

PipeRench Implementation of the Instruction Path Coprocessor / Y. Chou, P. Pillai, H. Schmit, J. P. Shen 147

Efficient Conditional Operations for Data-Parallel Architectures / U. J. Kapasi, W. J. Dally, S. Rixner, P. R. Mattson, J. D. Owens, B. Khailany 159

Flexible Hardware Acceleration for Multimedia Oriented Microprocessors / F. Vermeulen, L. Nachtergaele, F. Catthoor, D. Verkest, H. De Man 171

Low-Power Design / Rajiv Gupta

Very Low Power Pipelines Using Significance Compression / R. Canal, A. Gonzalez, J. E. Smith 181

A Static Power Model for Architects / J. A. Butts, G. S. Sohi 191

A Framework for Dynamic Energy Efficiency and Temperature Management / M. Huang, J. Renau, S.-M. Yoo, J. Torrellas 202

Dynamic Zero Compression for Cache Energy Reduction / L. Villa, M. Zhang, K. Asanovic 214

Memory Hierarchy II / Mike Smith

Register Integration: A Simple and Efficient Implementation of Squash Reuse / A. Roth, G. S. Sohi 223

The Store-Load Address Table and Speculative Register Promotion / M. Postiff, D. Greene, T. Mudge 235

Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures / R. Balasubramonian, D. Albonesi, A. Buyuktosunoglu, S. Dwarkadas 245

Frequent Value Compression in Data Caches / J. Yang, Y. Zhang, R. Gupta 258

Dynamic Translation and Multithreading / Kemal Ebcioglu

A Study of Slipstream Processors / Z. Purser, K. Sundaramoorthy, E. Rotenberg 269

Relational Profiling: Enabling Thread-Level Parallelism in Virtual Machines / T. Heil, J. E. Smith 281

Calpa: A Tool for Automating Selective Dynamic Compilation / M. Mock, C. Chambers, S. J. Eggers 291

Increasing the Size of Atomic Instruction Blocks Using Control Flow Assertions / S. J. Patel, T. Tung, S. Bose, M. M. Crum 303

Superscalar Architecture II / Bob Colwell

Reducing Wire Delay Penalty through Value Prediction / J.-M. Parcerisa, A. Gonzalez 317

Compiler Controlled Value Prediction Using Branch Predictor Based Confidence / E. Larson, T. Austin 327

Instruction Distribution Heuristics for Quad-Cluster, Dynamically-Scheduled, Superscalar Processors / A. Baniasadi, A. Moshovos 337

Performance Improvement with Circuit-Level Speculation / T. Liu, S.-L. Lu 348.

Notes:

"IEEE Computer Society Order Number PR00924"--T.p. verso.

Includes bibliographical references and index.

ISBN:

076950924X

9780769509242

0769509266

9780769509266

OCLC:

45693464

Access Restriction:

Restricted for use by site license.