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Proceedings. 32nd Annual International Symposium on Microarchitecture : Haifa, Israel, November 16-18, 1999 / sponsored by IEEE TC-MARCH, ACM SIGMICRO, with the generous support of Intel ... [and others].
- Format:
- Book
- Conference/Event
- Conference Name:
- Annual International Symposium on Microarchitecture (32nd : 1999 : Haifa, Israel)
- Series:
- ACM Digital Library (Series)
- Language:
- English
- Subjects (All):
- Computer architecture--Congresses.
- Computer architecture.
- Microprogramming--Congresses.
- Microprogramming.
- Genre:
- Conference papers and proceedings.
- Physical Description:
- xiii, 299 pages : illustrations
- Other Title:
- MICRO-32
- 32nd Annual International Symposium on Microarchitecture
- Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture
- Microarchitecture, 1999, MICRO-32, proceedings, 32nd Annual International Symposium on.
- Place of Publication:
- Los Alamitos, Calif. : IEEE Computer Society, [1999]
- System Details:
- Mode of access: World Wide Web.
- text file
- Contents:
- New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies / F. Pollack 2
- Session 2 Faster FrontEnd / Gary Tyson
- Control Independence in Trace Processors / E. Rotenberg, J. Smith 4
- Fetch Directed Instruction Prefetching / G. Reinman, B. Calder, T. Austin 16
- Improving Branch Predictors by Correlating on Data Values / T. Heil, Z. Smith, J. Smith 28
- Instruction Fetch Mechanisms for Multipath Execution Processors / A. Klauser, D. Grunwald 38
- Session 3 3D and MultiMedia / Matthew Farrens
- A Superscalar 3D Graphics Engine / A. Wolfe, D. Noonburg 50
- Dynamic 3D Graphics Workload Characterization and the Architectural Implications / T. Mitra, T. Chiueh 62
- Exploiting a New Level of DLP in Multimedia Applications / J. Corbal, R. Espasa, M. Valero 72
- Session 4 Efficient Embedded Processors / Kemal Ebcioglu
- Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors / S. Larin, T. Conte 82
- Evaluation of a High Performance Code Compression Method / C. Lefurgy, E. Piccininni, T. Mudge 93
- Low-Cost Branch Folding for Embedded Applications with Small Tight Loops / L. Lee, J. Scott, B. Moyer, J. Arends 103
- Session 5 Memory Hierarchy / Doug Burger
- Automatic and Efficient Evaluation of Memory Hierarchies for Embedded Systems / S. Abraham, S. Mahlke 114
- Hardware Identification of Cache Conflict Misses / J. Collins, D. Tullsen 126
- Access Region Locality for High-Bandwidth Processor Memory System Design / S. Cho, P. Yew, G. Lee 136
- Code Transformations to Improve Memory Parallelism / V. Pai, S. Adve 147
- Session 6 Better Scheduling / Stephan Jourdan
- Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results / D. Connors, W. Hwu 158
- Dynamic Memory Disambiguation in the Presence of Out-of-Order Store Issuing / S. Onder, R. Gupta 170
- Read-After-Read Memory Dependence Prediction / A. Moshovos, G. Sohi 177
- Delaying Physical Register Allocation through Virtual-Physical Registers / T. Monreal, A. Gonzalez, M. Valero, J. Gonzalez, V. Vinals 186
- Session 7 Invited Speaker / Gabby Silberman
- Core Technologies in Hardware and Software / B. Shriver 194
- Session 8 Novel Microarchitectures and Multithreading / Brad Calder
- DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design / T. Austin 196
- Exploiting ILP in Page-based Intelligent Memory / M. Oskin, J. Hensley, D. Keen, F. Chong, M. Farrens, A. Chopra 208
- The Use of Multithreading for Exception Handling / C. Zilles, J. Emer, G. Sohi 219
- Value Prediction for Speculative Multithreaded Architectures / P. Marcuello, J. Tubella, A. Gonzalez 230
- Session 9 Low Power Enhancements / Mateo Valero
- Predicting the Usefulness of a Block Result: A Micro-Architectural Technique for High-Performance Low-Power Processors / E. Musoll 238
- Selective Cache Ways: On-Demand Cache Resource Allocation / D. Albonesi 248
- Session 10 Compilers / David Bernstein
- Wavefront Scheduling: Path based Data Representation and Scheduling of Subgraphs / J. Bharadwaj, K. Menezes, C. McKinsey 262
- Balance Scheduling: Weighting Branch Tradeoffs in Superblocks / A. Eichenberger, W. Meleis 272
- Optimizations and Oracle Parallelism with Dynamic Translation / K. Ebcioglu, E. Altman, S. Sathaye, M. Gschwind 284.
- Notes:
- "IEEE Catalog Number PR00437"--T.p. verso.
- Includes bibliographical references and author index.
- ISBN:
- 076950437X
- 9780769504377
- 0769504388
- 9780769504384
- 0769504396
- 9780769504391
- OCLC:
- 43164212
- Access Restriction:
- Restricted for use by site license.
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