Adaptive techniques for dynamic processor optimization : theory and practice / edited by Alice Wang and Samuel Naffziger.

Format:

Book

Contributor:

Wang, Alice, 1975-

Naffziger, Samuel

Hazel M. Hussong Fund.

Series:

Series on integrated circuits and systems

Language:

English

Subjects (All):

High performance processors--Design and construction.

High performance processors.

Physical Description:

xvi, 304 pages : illustrations ; 25 cm.

Place of Publication:

New York ; London : Springer, 2008.

Summary:

Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice collects, in one place, the research and experience of pioneers in the burgeoning area of dynamically adaptive silicon, where the part optimizes itself "on the fly". Static and potentially unique configuration of each manufactured part has been practiced for some time, but advanced silicon processes no longer allow high performance parts that luxury. Variations, environmental conditions and diverse operating modes all confer a great competitive advantage on chips that succeed at monitoring conditions and adapting their operating point to optimize speed, power and reliability. This book discusses the different approaches and responses to adaptive techniques used for processor power, frequency and functionality optimization. Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice includes chapter contributions that explore promising approaches and present the supporting data.

This book is written for engineers interested in adaptive techniques for processors.

Contents:

Chapter 1 Technology Challenges Motivating Adaptive Techniques / David Scott, Alice Wang 1

1.1 Introduction 1

1.2 Motivation for Adaptive Techniques 2

1.2.1 Components of Power 2

1.2.2 Relation Between Frequency and Voltage 2

1.2.3 Control Loop Implementation 4

1.2.4 Practical Considerations 4

1.2.5 Impact of Temperature and Supply Voltage Variations 7

1.3 Technology Issues Relating to Performance-Enhancing Techniques 9

1.3.1 Threshold Voltage Variation 9

1.3.2 Random Dopant Fluctuations 11

1.3.3 Design in the Presence of Threshold Voltage Variation 13

1.4 Technology Issues Associated with Leakage Reduction Techniques 14

1.4.1 Practical Considerations 15

1.4.2 Sources of Leakage Current 16

1.4.3 Transistor Design for Low Leakage 20

1.5 Conclusion 21

References 21

Chapter 2 Technological Boundaries of Voltage and Frequency Scaling for Power Performance Tuning / Maurice Meijer, Jose Pineda de Gyvez 25

2.1 Adaptive Power Performance Tuning of ICs 25

2.2 AVS- and ABB-Scaling Operations 28

2.3 Frequency Scaling and Tuning 31

2.4 Power and Frequency Tuning 33

2.5 Leakage Power Control 37

2.6 Performance Compensation 40

2.7 Conclusion 44

References 46

Chapter 3 Adaptive Circuit Technique for Managing Power Consumption / Tadahiro Kuroda, Takayasu Sakurai 49

3.1 Introduction 49

3.2 Adaptive VDDControl 50

3.2.1 Dynamic Voltage Scaling 50

3.2.2 Frequency and Voltage Hopping 51

3.3 Adaptive VTHControl 55

3.3.1 Reverse Body Bias (VTCMOS) 55

3.3.1.1 Self-Adjusting Threshold Voltage (SAT) Scheme 55

3.3.1.2 Leakage Current Monitor 56

3.3.1.3 VTHControllability 57

3.3.1.4 Device Perspective 59

3.3.2 Forward Body Bias 60

3.3.3 Control Method and Granularity 61

3.3.4 VTHControl Under Variations 64

3.3.5 VTHControl vs. VDDControl 66

3.4 Hardware and Software Cooperative Control 68

3.4.1 Cooperation Between Hardware and Application Software 68

3.4.2 Cooperation Between Hardware and Operating System 70

3.5 Conclusion 71

References 71

Chapter 4 Dynamic Adaptation Using Body Bias, Supply Voltage, and Frequency / James Tschanz 75

4.1 Introduction 75

4.2 Static Compensation with Body Bias and Supply Voltage 76

4.2.1 Adaptive Body Bias 77

4.2.2 Adaptive Supply Voltage 82

4.3 Dynamic Variation Compensation 84

4.3.1 Dynamic Body Bias 84

4.3.2 Dynamic Supply Voltage, Body Bias, and Frequency 87

4.3.2.1 Design Details 87

4.3.2.2 Measurement Results 89

4.4 Conclusion 92

References 92

Chapter 5 Adaptive Supply Voltage Delivery for Ultra-Dynamic Voltage Scaled Systems / Yogesh K. Ramadass, Joyce Kwong, Naveen Verma, Anantha Chandrakasan 95

5.1 Logic Design for U-DVS Systems 97

5.1.1 Device Sizing 98

5.1.2 Timing Analysis 100

5.2 SRAM Design for Ultra Scalable Supply Voltages 101

5.2.1 Low-Voltage Bit-Cell Design 104

5.2.2 Periphery Design 105

5.3 Intelligent Power Delivery 107

5.3.1 Deriving VDDfor Given Speed Requirement 107

5.3.2 DC-DC Converter Topologies for U-DVS 109

5.3.2.1 Linear Regulators 109

5.3.2.2 Inductor Based DC-DC Converter 109

5.3.2.3 Switched Capacitor Based DC-DC Converter 110

5.3.3 DC-DC Converter Design and Reference Voltage Selection for Highly Energy-Constrained Applications 112

5.3.3.1 Minimum Energy Tracking Loop 113

5.4 Conclusion 119

References 120

Chapter 6 Dynamic Voltage Scaling with the XScale Embedded Microprocessor / Lawrence T. Clark, Franco Ricci, William E. Brown 123

6.1 The XScale Microprocessor 123

6.1.1 Chapter Overview 124

6.1.2 XScale Micro-Architecture Overview 125

6.1.3 Dynamic Voltage Scaling 126

6.1.4 The Performance Measurement Unit 127

6.2 Dynamic Voltage Scaling on the XScale Microprocessor 129

6.2.1 Running DVS 130

6.3 Impact of DVS on Memory Blocks 134

6.3.1 Guaranteeing SRAM Stability with DVS 134

6.4 PLL and Clock Generation Considerations 138

6.4.1 Clock Generation for DVS on the 180 nm 80200 XScale Microprocessor 138

6.4.2 Clock Generation 90 nm XScale Microprocessor 139

6.5 Conclusion 142

References 142

Chapter 7 Sensors for Critical Path Monitoring / Alan Drake 145

7.1 Variability and its Impact on Timing 145

7.2 What Is a Critical Path 147

7.3 Sources of Path Delay Variability 148

7.3.1 Process Variation 149

7.3.2 Environmental Variation 149

7.4 Timing Sensitivity of Path Delay 151

7.5 Critical Path Monitors 158

7.5.1 Synchronizer 158

7.5.2 Delay Path Configuration 159

7.5.3 Time-to-Digital Conversion 163

7.5.3.1 Sensitivity 167

7.5.4 Control and Calibration 168

7.6 Conclusion 169

Acknowledgements 171

References 171

Chapter 8 Architectural Techniques for Adaptive Computing / Shidhartha Das, David Roberts, David Blaauw, David Bull, Trevor Mudge 175

8.1 Introduction 175

8.1.1 Spatial Reach 177

8.1.2 Temporal Rate of Change 177

8.2 "Always Correct" Techniques 179

8.2.1 Look-up Table-Based Approach 179

8.2.2 Canary Circuits-Based Approach 180

8.2.3 In situ Triple-Latch Monitor 181

8.2.4 Micro-architectural Techniques 182

8.3 Error Detection and Correction Approaches 183

8.3.1 Techniques for Communication and Signal Processing 184

8.3.2 Techniques for General-Purpose Computing 186

8.4 Introduction to Razor 187

8.4.1 Razor Error Detection and Recovery Scheme 188

8.4.2 Micro-architectural Recovery 190

8.4.2.1 Recovery Using Clock-Gating 190

8.4.2.2 Recovery Using Counter-Flow Pipelining 191

8.4.3 Short-Path Constraints 192

8.4.4 Circuit-Level Implementation Issues 192

8.5 Silicon Implementation and Evaluation of Razor 195

8.5.1 Measurement Results 196

8.5.2 Total Energy Savings with Razor 197

8.5.3 Razor Voltage Control Response 199

8.6 Ongoing Razor Research 200

8.7 Conclusion 202

References 203

Chapter 9 Variability-Aware Frequency Scaling in Multi-Clock Processors / Sebastian Herbert, Diana Marculescu 207

9.1 Introduction 207

9.2 Addressing Process Variability 209

9.2.1 Approach 209

9.2.2 Combinational Logic Variability Modeling 212

9.2.3 Array Structure Variability Modeling 213

9.2.4 Application to the Frequency Island Processor 215

9.3 Addressing Thermal Variability 217

9.4 Experimental Setup 218

9.4.1 Baseline Simulator 218

9.4.2 Frequency Island Simulator 219

9.4.3 Benchmarks Simulated 219

9.5 Results 220

9.5.1 Frequency Island Baseline 220

9.5.2 Frequency Island with Critical Path Information 221

9.5.3 Frequency Island with Thermally Aware Frequency Scaling 222

9.5.4 Frequency Island with Critical Path Information and Thermally Aware Frequency Scaling 224

9.6 Conclusion 225

Acknowledgements 225

References 225

Chapter 10 Temporal Adaptation - Asynchronicity in Processor Design / Steve Furber, Jim Garside 229

10.1 Introduction 229

10.2 Asynchronous Design Styles 230

10.3 Asynchronous Adaptation to Workload 232

10.4 Data Dependent Timing 234

10.5 Architectural Variation in Asynchronous Systems 237

10.5.1 Adapting the Latch Style 237

10.5.2 Controlling the Pipeline Occupancy 240

10.5.3 Reconfiguring the Microarchitecture 241

10.6 Benefits of Asynchronous Design 244

10.7 Conclusion 245

References 245

Chapter 11 Dynamic and Adaptive Techniques in SRAM Design / John J. Wuu 249

11.1 Introduction 249

11.2 Read and Write Margins 250

11.2.1 Voltage Optimization Techniques 251

11.2.1.1 Column Voltage Optimization 252

11.2.1.2 Row Voltage Optimization 255

11.2.2 Timing Control 257

11.3 Array Power Reduction 259

11.3.1 Sleep Types 259

11.3.1.1 Active Sleep 260

11.3.1.2 Passive Sleep 261

11.3.2 P Versus N Sleep 263

11.3.3 Entering and Exiting Sleep 264

11.3.4 Dynamic Cache Power Down 266

11.3.5 Data Bus Encoding 266

11.4 Reliability 267

11.4.1 Soft Errors 267

11.4.2 Hard Errors 267

11.4.2.1 Cache Line Disable 268

11.4.2.2 Cache Line Remap 268

11.4.2.3 Defect Correction 268

11.5 Conclusion 269

References 270

Chapter 12 The Challenges of Testing Adaptive Designs / Eric Fetzer, Jason Stinson, Brian Cherkauer, Steve Poehlman 273

12.1 The Adaptive Features of the Itanium 2 9000 Series 273

12.1.1 Active De-skew 273

12.1.2 Cache Safe Technology 277

12.1.3 Foxton Technology 278

12.2 The Path to Production 281

12.2.1 Fundamentals of Testing with Automated Test Equipment (ATE) 281

12.2.2 Manufacturing Test 281

12.2.3 Class or Package Testing 283

12.2.4 System Testing 285

12.3 The Impact of Adaptive Techniques on Determinism and Repeatability 286

12.3.1 Validation of Active De-skew 287

12.3.2 Testing of Active De-skew 290

12.3.3 Testing of Power Measurement 291

12.3.4 Power Measurement Impacts on Other Testing 294

12.3.5 Test Limitations and Guard-Banding 296

12.4 Guard-Band Concerns of Adaptive Power Management 297

12.5 Conclusion 300

References 300.

Notes:

Includes bibliographical references and index.

Local Notes:

Acquired for the Penn Libraries with assistance from the Hazel M. Hussong Fund.

ISBN:

9780387764719

0387764712

OCLC:

180470537