Low-power high-level synthesis for nanoscale CMOS circuits / Saraju P. Mohanty ... [and others].

Format:

Book

Contributor:

Mohanty, Saraju P.

Language:

English

Subjects (All):

Metal oxide semiconductors, Complementary.

Low voltage integrated circuits.

Nanotechnology.

Physical Description:

xxxii, 302 pages : illustrations ; 25 cm

Place of Publication:

New York : Springer, [2008]

Summary:

Low-Power High-Level Synthesis for Nanoscale CMOS Circuits addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation because the behavioral level is not as highly abstracted as the system level nor is it as complex as the gate/transistor level. At the behavioral level there is a balanced degree of freedom to explore power reduction mechanisms, the power reduction opportunities are greater, and it can cost-effectively help in investigating lower power design alternatives prior to actual circuit layout or silicon implementation.

The book is a self-contained low-power, high-level synthesis text for Nanoscale VLSI design engineers and researchers. Each chapter has simple relevant examples for a better grasp of the principles presented. Several algorithms are given to provide a better understanding of the underlying concepts. The initial chapters deal with the basics of high-level synthesis, power dissipation mechanisms, and power estimation. In subsequent parts of the text, a detailed discussion of methodologies for the reduction of different types of power is presented including: Power Reduction Fundamentals, Energy or Average Power Reduction, Peak Power Reduction, Transient Power Reduction, Leakage Power Reduction. Low-Power High-Level Synthesis for Nanoscale CMOS Circuits provides a valuable resource for the design of low-power CMOS circuits.

Contents:

2 High-Level Synthesis Fundamentals 5

2.2 The Complete Chip Story: From Customers' Requirements to Silicon Chips for Customers 5

2.3 Various Phases of Circuit Design and Synthesis 7

2.4 High-Level or Behavioral Synthesis: What and Why 10

2.5 Various Phases of High-Level Synthesis 11

2.5.1 Compilation 12

2.5.2 Transformation 12

2.5.3 Scheduling 13

2.5.4 Selection or Allocation 13

2.5.5 Binding or Assignment 13

2.5.6 Output Generation 14

2.5.7 A Demonstrative Example 14

2.6 Behavioral HDL to CDFG Translation or Compilation 14

2.7 Scheduling Algorithms 16

2.7.1 ASAP and ALAP Scheduling and Mobility 19

2.7.2 Integer Linear Programming (ILP) Scheduling 19

2.7.3 List-Based Scheduling (LBS) 23

2.7.4 Force-Directed Scheduling (FDS) 25

2.7.5 Game Theory Scheduling (GTS) 26

2.7.6 Tabu Search Scheduling (TSS) 28

2.7.7 Simulated Annealing Scheduling (SAS) 29

2.7.8 Genetic Algorithm Scheduling (GAS) 30

2.7.9 Ant Colony Scheduling (ACS) 30

2.7.10 Automata-Based Symbolic Scheduling 31

2.7.11 Chaining, Multicycling and Pipelining Data Paths 31

2.8 Binding or Allocations Algorithms 32

2.8.1 Clique Partitioning Approach 33

2.8.2 Graph Coloring Approach 33

2.8.3 Left Edge Algorithm for Register Optimization 35

2.8.4 Integer Linear Programming (ILP) Binding 36

2.8.5 Heuristic Algorithm to Solve Clique Partitioning 37

2.8.6 GTS Algorithm 37

2.9 Control Synthesis 38

2.10 High-Level Synthesis Benchmarks 38

2.11 High-Level Synthesis Tools 44

2.11.1 CatapultC from Mentor Graphics 44

2.11.2 CyberWorkBench from NEC 44

2.11.3 PICO Express from Synfora 44

2.11.4 Cynthesizer from Forte Design Systems 44

2.11.5 Cascade from Critical Blue 45

2.11.6 Agility Compiler from Celoxica 45

2.11.7 eXCite from Y Explorations 45

2.11.8 ESEComp from BlueSpec 45

2.11.9 VCS from Synopsys 45

2.11.10 NC-SC, NC-Verilog and NC-VHDL from Cadence 45

2.11.11 Synplify from Synplicity 46

2.11.12 ISE from Xilinx 46

2.11.13 Quartus from Altera 46

3 Power Modeling and Estimation at Transistor and Logic Gate Levels 47

3.2 CMOS Technology Trends 48

3.3 Current Conduction Mechanisms in Nano-CMOS Devices: A Resume 49

3.3.1 The Ideal ON and OFF States 49

3.3.2 Junction Reverse Bias Current 50

3.3.3 Drain-Induced Barrier Lowering (DIBL) 51

3.3.4 Subthreshold Leakage 51

3.3.5 Gate-Induced Drain Leakage (GIDL) 52

3.3.6 Punch-Through 53

3.3.7 Hot-Carrier Injection 53

3.3.8 Band-to-Band Tunneling (BTBT) 54

3.3.9 Gate-Oxide Tunneling 55

3.4 Power Dissipation in Nano-CMOS Logic Gates 59

3.4.1 Static, Dynamic and Leakage Power Dissipation 59

3.4.2 Case Study: The 45 nm NOT, NAND, NOR CMOS Gates 60

3.5 Process Variation Effects 67

3.5.1 Origins and Sources of Process Variation 67

3.5.2 Methodologies to Accommodate Process Variation 68

3.6 From Gates to Functional Units: A Power Modeling and Estimation Perspective 72

3.6.1 SPICE level 73

3.6.2 Probabilistic and Statistical Techniques 75

4 Architectural Power Modeling and Estimation 81

4.2 Architecture-Level Estimation 84

4.3 Dynamic Power Modeling and Estimation 90

4.3.1 Abstract Data Path Power Estimation 91

4.3.2 Capacitance Estimation 92

4.3.3 Macro-modeling for Dynamic Power 93

4.3.4 Estimation of Bounds on Average Power 94

4.4 Leakage Modeling 94

4.4.1 Subthreshold and Gate-Oxide Leakage Power Modeling and Estimation 95

4.4.2 Methods for Total Leakage Estimation 97

4.5 Modeling and Analysis of Architectural Components 100

4.5.1 Design-Optimization-Aware Estimation 100

4.5.2 Estimating Under Variation Effects 103

4.5.3 Estimating Power in Control and Data Path Logic 104

4.5.4 Communication Components 106

4.6 Register Files 108

4.6.1 Methodology 109

4.6.2 Basic Power Model 109

4.6.3 Pipelined Register Files 111

4.6.4 Physical Dimensions and Latency 11

4.6.5 Area, Power, Delay Models 115

4.6.6 Device Sizing 119

4.7 Cache Arrays 120

4.7.1 CACTI Dynamic Power Model for Caches 120

4.7.2 Leakage Modeling for Arrays 123

4.8 Validation and Accuracy 125

4.8.1 Model Validation: Arrays as an Example 125

4.8.2 Simulator Accuracy 127

4.8.3 Power Model Accuracy 127

4.9 Effect of Temperature on Power 128

5 Power Reduction Fundamentals 131

5.2 Power Dissipation or Consumption Profile of CMOS Circuits 131

5.3 Why Low-Power Design? 133

5.4 Why Energy or Average Power Reduction? 135

5.5 Why Peak Power Minimization? 136

5.6 Why Transient Power Minimization? 137

5.7 Why Leakage Power Minimization? 137

5.8 Power Reduction Mechanisms at Different Levels of Abstraction 138

5.9 Why Power Optimization During High-Level or Behavioral Synthesis? 138

5.10 Methods for Power Reduction in High-Level Synthesis 139

5.11 Frequency and/or Voltage Scaling for Dynamic Power Reduction 140

5.11.1 What Is Voltage or Frequency Scaling? 140

5.11.2 Why Frequency and/or Voltage Scaling? 142

5.11.3 Energy or Average Power Reduction Using Voltage or Frequency Scaling 143

5.11.4 Peak Power Reduction Using Voltage and Frequency Scaling 145

5.11.5 Issues in Multiple Supply Voltage-Based Design 146

5.11.6 Voltage-Level Converter Design 146

5.11.7 Dynamic Frequency Clocking Unit Design 148

5.12 V[subscript Th] Scaling for Subthreshold Leakage Reduction 150

5.12.2 Multiple Threshold CMOS (MTCMOS) Technology 151

5.12.3 Variable Threshold CMOS (VTCMOS) Technology 152

5.12.4 Dynamic Threshold CMOS (DTCMOS) Technology 152

5.12.5 Leakage Control Transistor (LECTOR) Technique 152

5.12.6 The Issues 153

5.13 T[subscript ox], K or L Scaling for Gate-Oxide Leakage Reduction 153

5.13.2 Multiple Oxide Thickness CMOS (MOXCMOS) Technology 154

5.13.3 Multiple Dielectric (k) (MKCMOS) Technology 154

5.13.4 The Issues 154

5.14 Transformation Techniques for Power Reduction 155

5.14.1 Operation Reduction 155

5.14.2 Operation Substitution 156

5.15 Increased Parallelism and Pipelining with Architecture-Driven Voltage Scaling for Power Reduction 156

5.15.1 Parallelism with Voltage Scaling 157

5.15.2 Pipelining with Voltage Scaling 157

5.16 Guarded Evaluation to Reduce Power 159

5.17 Precomputation-Based Power Reduction 160

5.18 Clock Gating to Reduce Clock Power Dissipation 161

5.19 Interconnect Power Minimization 161

6 Energy or Average Power Reduction 163

6.2 Target Architecture and Data Path Specifications for Multiple Voltage 164

6.3 ILP-Based Scheduling for EDP Reduction 165

6.3.2 EDP Modeling of a DFG 166

6.3.3 ILP Formulations for EDPs 168

6.3.4 ILP-Based Data Path Scheduling Algorithm 170

6.3.5 Experimental Results 172

6.4 Heuristic-Based Scheduling Algorithm for Energy Minimization 176

6.4.2 Time-Constrained Scheduling: TC-DFC 177

6.4.3 Resource-Constrained Scheduling: RC-DFC 183

6.4.4 Experimental Results 188

6.5 Data Path Scheduling for Energy or Average Power Reduction Using Voltage Reduction 191

6.5.1 Time- or Resource-Constrained Scheduling Algorithms 191

6.5.2 Time- and Resource-Constrained Scheduling Algorithms 193

6.6 Switching Activity Reduction During High-Level Synthesis 194

6.6.1 Scheduling and/or Allocation for Switching Activity Reduction 195

6.6.2 Scheduling and/or Binding for Switching Activity Reduction 198

7 Peak Power Reduction 201

7.2 Peak and Average Power Dissipation Modeling of a Data Path Circuit 201

7.3 ILP-Based Scheduling for Peak Power Reduction 204

7.3.1 ILP Formulations 205

7.3.2 ILP-Based Scheduler 207

7.3.3 Experimental Results 211

7.4 ILP-Based Scheduling for Simultaneous Peak and Average Power Reduction 215

7.4.1 ILP Formulations 215

7.4.2 ILP-Based Scheduler 216

7.4.3 Experimental Results 219

7.5 Scheduling or Binding for Peak Power Reduction 222

7.5.1 Scheduling Algorithms 222

7.5.2 Binding

Algorithms 223

8 Transient Power Reduction 225

8.2 Modeling for Power Transience or Fluctuation of a Data Path Circuit 225

8.2.1 Model 1: CPF Using Mean Deviation 226

8.2.2 Model 2: CPF Using Cycle-to-Cycle Gradient 229

8.2.3 Minimization of CPF as an Objective Function 230

8.3 Heuristic-Based Scheduling Algorithm for CPF Minimization 232

8.3.2 Algorithm Flow 232

8.3.3 Pseudocode of the Algorithm Heuristic 234

8.3.4 Algorithm Time Complexity 236

8.3.5 Experimental Results 236

8.4 Modified Cycle Power Function (CPF*) 242

8.5 Linear Programming Modeling of Non-linearities 244

8.5.1 Linear Programming Formulation Involving the Sum of Absolute Deviations 244

8.5.2 Linear Programming Formulation Involving Fractions 245

8.6 ILP Formulations to Minimize (CPF*) 246

8.6.1 For MVDFC Operation 246

8.6.2 For MVMC Operation 249

8.7 ILP-Based Scheduling Algorithm for CPF* Minimization 251

8.7.2 Algorithm 252

8.7.3 Experimental Results 254

8.8 Data Monitoring for Transient Power Minimization 259

9 Leakage Power Reduction 261

9.2 Gate-Oxide Leakage Reduction 262

9.2.1 Dual-T[subscript ox] Technique 262

9.2.2 Dual-k Technique 271

9.3 Subthreshold Leakage Reduction 274

9.3.1 Prioritization Algorithm for Dual-V[subscript Th]-Based Optimization 274

9.3.2 MTCMOS-Based Clique Partitioning for Subthreshold Leakage Reduction 275

9.3.3 MTCMOS-Based Knapsack Binding for Subthreshold Leakage Reduction 275

9.3.4 Power Island Technique for Subthreshold Leakage Reduction 276

9.3.5 Maximum Weight-Independent Set (MWIS) Problem Heuristic for Dual-V[subscript Th]-Based Optimization 276

10 Conclusions and Future Directions 277.

Notes:

Includes bibliographical references (pages 281-298) and index.

ISBN:

9780387764733

0387764739

OCLC:

209335825