The essentials of computer organization and architecture / Linda Null and Julia Lobur.

Format:

Book

Author/Creator:

Null, Linda.

Contributor:

Lobur, Julia.

Louis A. Duhring Fund.

Language:

English

Subjects (All):

Computer organization.

Computer architecture.

Physical Description:

xxxii, 799 pages : illustrations ; 24 cm

Edition:

Second edition.

Place of Publication:

Sudbury, Mass. : Jones and Bartlett Publishers, [2006]

Summary:

Thoroughly, revised and updated, this second edition of The Essentials of Computer Organization and Architecture is a comprehensive resource that addresses all of the necessary organization and architecture topics, yet is concise enough to cover in a single semester. Created in direct correlation to the ACM-IEEE Computing Curricula 2001 guidelines, this text exposes the inner workings of a modern digital computer through an integrated presentation of fundamental concepts and principles. The authors present real-world examples and focus on practical applications, thus encouraging students to develop a "big- picture" understanding of how essential organization and architecture concepts are applied in the world of computing.

New and Key Features of the Second Edition: Includes a new chapter on Embedded Systems, Correlates to the ACM-IEEE Computing Curricula 2001 guidelines, Presents in-depth coverage of the appropriate core concepts, yet still provides the necessary exposure to less critical concepts, thus allowing students to see the whole picture, Includes the following: Comprehensive presentation of I/O, including Raid devices, data compression, and future directions in storage technology, An easy, yet precise, introduction to cache memories and paging, Coverage of various architectures, including RISC, superscalar, parallel, neural networks, distributed, and dataflow, Now Available - A new Intel supplement for students (ISBN 0-7637-3585-X) allows instructors to cover assembly language in more depth.

Contents:

1.2 The Main Components of a Computer 3

1.3 An Example System: Wading Through the Jargon 4

1.4 Standards Organizations 13

1.5 Historical Development 14

1.5.1 Generation Zero: Mechanical Calculating Machines (1642-1945) 15

1.5.2 The First Generation: Vacuum Tube Computers (1945-1953) 17

1.5.3 The Second Generation: Transistorized Computers (1954-1965) 21

1.5.4 The Third Generation: Integrated Circuit Computers (1965-1980) 24

1.5.5 The Fourth Generation: VLSI Computers (1980-????) 24

1.5.6 Moore's Law 27

1.6 The Computer Level Hierarchy 28

1.7 The von Neumann Model 30

1.8 Non-von Neumann Models 32

Chapter 2 Data Representation in Computer Systems 39

2.2 Positional Numbering Systems 40

2.3 Decimal to Binary Conversions 40

2.3.1 Converting Unsigned Whole Numbers 41

2.3.2 Converting Fractions 43

2.3.3 Converting between Power-of-Two Radices 46

2.4 Signed Integer Representation 46

2.4.1 Signed Magnitude 46

2.4.2 Complement Systems 52

2.4.3 Unsigned Versus Signed Numbers 58

2.4.4 Computers, Arithmetic, and Booth's Algorithm 58

2.4.5 Carry Versus Overflow 62

2.5 Floating-Point Representation 63

2.5.1 A Simple Model 64

2.5.2 Floating-Point Arithmetic 66

2.5.3 Floating-Point Errors 67

2.5.4 The IEEE-754 Floating-Point Standard 68

2.5.5 Range, Precision, and Accuracy 71

2.5.6 Additional Problems with Floating-Point Numbers 71

2.6 Character Codes 74

2.6.1 Binary-Coded Decimal 74

2.6.2 EBCDIC 76

2.6.3 ASCII 78

2.6.4 Unicode 80

2.7 Error Detection and Correction 81

2.7.1 Cyclic Redundancy Check 81

2.7.2 Hamming Codes 84

2.7.3 Reed-Soloman 90

Chapter 3 Boolean Algebra and Digital Logic 109

3.2 Boolean Algebra 110

3.2.1 Boolean Expressions 111

3.2.2 Boolean Identities 112

3.2.3 Simplification of Boolean Expressions 114

3.2.4 Complements 115

3.2.5 Representing Boolean Functions 116

3.3 Logic Gates 118

3.3.1 Symbols for Logic Gates 118

3.3.2 Universal Gates 119

3.3.3 Multiple Input Gates 120

3.4 Digital Components 121

3.4.1 Digital Circuits and Their Relationship to Boolean Algebra 121

3.4.2 Integrated Circuits 122

3.5 Combinational Circuits 123

3.5.2 Examples of Typical Combinational Circuits 124

3.6 Sequential Circuits 131

3.6.2 Clocks 131

3.6.3 Flip-Flops 132

3.6.4 Finite State Machines 135

3.6.5 Examples of Sequential Circuits 140

3.6.6 An Application of Sequential Logic: Convolutional Coding and Viterbi Detection 145

3.7 Designing Circuits 151

Chapter 4 MARIE: An Introduction to a Simple Computer 177

4.2 CPU Basics and Organization 177

4.2.1 The Registers 178

4.2.2 The ALU 179

4.2.3 The Control Unit 179

4.3 The Bus 179

4.4 Clocks 183

4.5 The Input/Output Subsystem 185

4.6 Memory Organization and Addressing 186

4.7 Interrupts 189

4.8 MARIE 190

4.8.1 The Architecture 190

4.8.2 Registers and Buses 190

4.8.3 Instruction Set Architecture 193

4.8.4 Register Transfer Notation 195

4.9 Instruction Processing 198

4.9.1 The Fetch-Decode-Execute Cycle 198

4.9.2 Interrupts and the Instruction Cycle 199

4.9.3 MARIE's I/O 203

4.10 A Simple Program 203

4.11 A Discussion on Assemblers 206

4.11.1 What Do Assemblers Do? 206

4.11.2 Why Use Assembly Language? 208

4.12 Extending our Instruction Set 209

4.13 A Discussion on Decoding: Hardwired Versus Microprogrammed Control 214

4.13.1 Machine Control 214

4.13.2 Hardwired Control 216

4.13.3 Microprogrammed Control 217

4.14 Real-World Examples of Computer Architectures 223

4.14.1 Intel Architectures 224

4.14.2 MIPS Architectures 230

Chapter 5 A Closer Look at Instruction Set Architectures 243

5.2 Instruction Formats 243

5.2.1 Design Decisions for Instruction Sets 244

5.2.2 Little Versus Big Endian 245

5.2.3 Internal Storage in the CPU: Stacks Versus Registers 247

5.2.4 Number of Operands and Instruction Length 248

5.2.5 Expanding Opcodes 252

5.3 Instruction Types 254

5.3.1 Data Movement 254

5.3.2 Arithmetic Operations 254

5.3.3 Boolean Logic Instructions 255

5.3.4 Bit Manipulation Instructions 255

5.3.5 Input/Output Instructions 256

5.3.6 Instructions for Transfer of Control 256

5.3.7 Special Purpose Instructions 256

5.3.8 Instruction Set Orthogonality 256

5.4 Addressing 257

5.4.1 Data Types 257

5.4.2 Address Modes 258

5.5 Instruction-Level Pipelining 261

5.6 Real-World Examples of ISAs 266

5.6.1 Intel 266

5.6.2 MIPS 267

5.6.3 Java Virtual Machine 267

Chapter 6 Memory 281

6.2 Types of Memory 281

6.3 The Memory Hierarchy 283

6.3.1 Locality of Reference 285

6.4 Cache Memory 285

6.4.1 Cache Mapping 287

6.4.2 Replacement Policies 295

6.4.3 Effective Access Time and Hit Ratio 296

6.4.4 When Does Caching Break Down? 297

6.4.5 Cache Write Policies 297

6.4.6 Instruction and Data Caches 300

6.4.7 Levels of Cache 301

6.5 Virtual Memory 302

6.5.1 Paging 303

6.5.2 Effective Access Time Using Paging 310

6.5.3 Putting It All Together: Using Cache, TLBs, and Paging 311

6.5.4 Advantages and Disadvantages of Paging and Virtual Memory 313

6.5.5 Segmentation 314

6.5.6 Paging Combined with Segmentation 315

6.6 A Real-World Example of Memory Management 316

Chapter 7 Input/Output and Storage Systems 327

7.2 I/O and Performance 328

7.3 Amdahl's Law 328

7.4 I/O Architectures 329

7.4.1 I/O Control Methods 331

7.4.2 Character I/O Versus Block I/O 338

7.4.3 I/O Bus Operation 338

7.5 Data Transmission Modes 341

7.5.1 Parallel Data Transmission 341

7.5.2 Serial Data Transmission 345

7.6 Magnetic Disk Technology 345

7.6.1 Rigid Disk Drives 347

7.6.2 Flexible (Floppy) Disks 351

7.7 Optical Disks 353

7.7.1 CD-ROM 353

7.7.2 DVD 357

7.7.3 Blue-Violet Laser Disks 358

7.7.4 Optical Disk Recording Methods 358

7.8 Magnetic Tape 359

7.9 RAID 364

7.9.1 RAID Level 0 365

7.9.2 RAID Level 1 366

7.9.3 RAID Level 2 366

7.9.4 RAID Level 3 367

7.9.5 RAID Level 4 368

7.9.6 RAID Level 5 369

7.9.7 RAID Level 6 370

7.9.8 RAID DP 371

7.9.9 Hybrid RAID Systems 372

7.10 The Future of Data Storage 372

Chapter 8 System Software 407

8.2 Operating Systems 408

8.2.1 Operating Systems History 409

8.2.2 Operating System Design 414

8.2.3 Operating System Services 416

8.3 Protected Environments 420

8.3.1 Virtual Machines 421

8.3.2 Subsystems and Partitions 424

8.3.3 Protected Environments and the Evolution of Systems Architectures 426

8.4 Programming Tools 428

8.4.1 Assemblers and Assembly 428

8.4.2 Link Editors 431

8.4.3 Dynamic Link Libraries 432

8.4.4 Compilers 434

8.4.5 Interpreters 438

8.5 Java: All of the Above 439

8.6 Database Software 445

8.7 Transaction Managers 451

Chapter 9 Alternative Architectures 461

9.2 RISC Machines 462

9.3 Flynn's Taxonomy 467

9.4 Parallel and Multiprocessor Architectures 471

9.4.1 Superscalar and VLIW 472

9.4.2 Vector Processors 474

9.4.3 Interconnection Networks 475

9.4.4 Shared Memory Multiprocessors 480

9.4.5 Distributed Computing 484

9.5 Alternative Parallel Processing Approaches 487

9.5.1 Dataflow Computing 487

9.5.2 Neural Networks 489

9.5.3 Systolic Arrays 492

9.6 Quantum Computing 494

Chapter 10 Topics in Embedded Systems 05

10.2 An Overview of Embedded Hardware 507

10.2.1 Off-the-Shelf Embedded System Hardware 507

10.2.2 Configurable Hardware 511

10.2.3 Custom-Designed Embedded Hardware 518

10.3 An Overview of Embedded Software 526

10.3.1 Embedded Systems Memory Organization 527

10.3.2 Embedded Operating Systems 528

10.3.3 Embedded Systems Software Development 531

Chapter 11 Performance Measurement

and Analysis 541

11.2 Computer Performance Equations 542

11.3 Mathematical Preliminaries 543

11.3.1 What the Means Mean 544

11.3.2 The Statistics and Semantics 549

11.4 Benchmarking 551

11.4.1 Clock Rate, MIPS, and FLOPS 552

11.4.2 Synthetic Benchmarks: Whetstone, Linpack, and Dhrystone 554

11.4.3 Standard Performance Evaluation Corporation Benchmarks 555

11.4.4 Transaction Processing Performance Council Benchmarks 559

11.4.5 System Simulation 566

11.5 CPU Performance Optimization 567

11.5.1 Branch Optimization 567

11.5.2 Use of Good Algorithms and Simple Code 570

11.6 Disk Performance 574

11.6.1 Understanding the Problem 574

11.6.2 Physical Considerations 575

11.6.3 Logical Considerations 576

Chapter 12 Network Organization and Architecture 591

12.2 Early Business Computer Networks 591

12.3 Early Academic and Scientific Networks: The Roots and Architecture of the Internet 592

12.4 Network Protocols I: ISO/OSI Protocol Unification 596

12.4.1 A Parable 597

12.4.2 The OSI Reference Model 598

12.5 Network Protocols II: TCP/IP Network Architecture 602

12.5.1 The IP Layer for Version 4 602

12.5.2 The Trouble with IP Version 4 606

12.5.3 Transmission Control Protocol 610

12.5.4 The TCP Protocol at Work 611

12.5.5 IP Version 6 615

12.6 Network Organization 622

12.6.1 Physical Transmission Media 622

12.6.2 Interface Cards 630

12.6.3 Repeaters 631

12.6.4 Hubs 631

12.6.5 Switches 632

12.6.6 Bridges and Gateways 633

12.6.7 Routers and Routing 634

12.7 High-Capacity Digital Links 643

12.7.1 The Digital Hierarchy 643

12.7.2 ISDN 648

12.7.3 Asynchronous Transfer Mode 651

12.8 A Look at the Internet 652

12.8.1 Ramping on to the Internet 653

12.8.2 Ramping up the Internet 660

Chapter 13 Selected Storage Systems and Interfaces 669

13.2 SCSI Architecture 670

13.2.1 "Classic" Parallel SCSI 671

13.2.2 The SCSI Architecture Model-3 675

13.3 Internet SCSI 682

13.4 Storage Area Networks 685

13.5 Other I/O Connections 685

13.5.1 Parallel Buses: XT to ATA 686

13.5.2 Serial ATA and Serial Attached SCSI 687

13.5.3 Peripheral Component Interconnect 688

13.5.4 A Serial Interface: USB 689

13.5.5 High Performance Peripheral Interface: HiPPI 689

Appendix A Data Structures and the Computer 695

A.2 Fundamental Structures 695

A.2.1 Arrays 695

A.2.2 Queues and Linked Lists 697

A.2.3 Stacks 698

A.3 Trees 701

A.4 Network Graphs 707.

Notes:

Includes bibliographical references and index.

Local Notes:

Acquired for the Penn Libraries with assistance from the Louis A. Duhring Fund.

ISBN:

0763737690

9780763737696

OCLC:

62282041