Test resource partitioning for system-on-a-chip / Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra.

Format:

Book

Author/Creator:

Chakrabarty, Krishnendu.

Contributor:

Iyengar, Vikram.

Chandra, Anshuman.

Series:

Frontiers in electronic testing ; 20.

Frontiers in electronic testing ; 20

Language:

English

Subjects (All):

Systems on a chip--Testing.

Systems on a chip.

Plug and play (Computer architecture).

Testing.

Physical Description:

xii, 232 pages : illustrations ; 25 cm.

Place of Publication:

Boston : Kluwer Academic Publishers, [2002]

Contents:

1. Test Resource Partitioning 3

1.1 System-on-a-chip: The new design philosophy 3

1.2 Testing a system-on-a-chip 5

1.2.1 Testing VLSI circuits 6

1.2.2 SOC test challenges 7

1.3 Test Resource Partitioning (TRP) 9

1.3.1 Classification of TRP techniques 10

Part II Trp for Test Hardware Optimization

2. Test Access Mechanism Optimization 19

2.2 Optimal assignment of cores to test buses 22

2.3 Optimal test bus width 28

2.5 Optimal subdivision of test buses 38

2.6 Future research 43

3. Improved Test Bus Partitioning 45

3.2 Improved test data de-serialization 48

3.3 Optimal test bus sizing 52

3.4 Test bus subdivision 57

3.5 Test bus sizing under routing and power constraints 59

3.5.1 Satisfying place-and-route constraints 59

3.5.2 Satisfying power constraints 61

4. Test Wrapper and Tam Co-Optimization 65

4.2 Prior work 67

4.3 Example SOCs 69

4.4 Test wrapper design 69

4.5 Optimal core assignment to TAMs 78

4.6 Optimal partitioning of TAM width 82

4.7 Enumerative TAM sizing 86

4.8 General problem of wrapper/TAM co-optimization 89

4.9 Future work 92

Part III TRP for Testing Time Minimization

5. Test Scheduling 97

5.2 Polynomial-time algorithm for test scheduling 100

5.3 Test scheduling: General case 106

5.4 Test scheduling with multiple test sets 113

5.5 Future research 116

6. Precedence, Preemption, and Power Constraints 119

6.2 Precedence-based scheduling 122

6.3 Preemptive scheduling 127

6.4 Power-constrained scheduling 131

Part IV TRP for Test Data Volume Reduction

7. Test Data Compression Using Golomb Codes 137

7.2 Golomb coding 142

7.3 Test data compression/decompression 148

7.3.1 Pattern decompression 150

7.3.2 Decompression architecture 152

7.3.3 Experimental results 157

7.4 TRP using internal scan chains and Golomb coding 163

7.4.1 Compression method and test architecture 164

7.4.2 Test application time and test data compression 167

7.4.3 Interleaving decompression architecture 171

7.4.4 Experimental results 176

8. Frequency-Directed Run-Length (FDR) Codes 179

8.2 FDR codes 180

8.3 Analysis of FDR codes 183

8.4 Extensions to the FDR code and test data decompression 191

8.5 Experimental results 195

9. TRP for Low-Power Scan Testing 203

9.2 Compression method and test architecture 206

9.3 Power estimation for scan vectors 208

9.4 Experimental results 212.

Notes:

Includes bibliographical references (pages [223]-229) and index.

ISBN:

1402071191

OCLC:

49751048