Asynchronous pulse logic / Mika Nyström, Alain J. Martin.

Format:

Book

Author/Creator:

Nyström, Mika.

Contributor:

Martin, Alain J.

Language:

English

Subjects (All):

Electronic digital computers--Circuits.

Electronic digital computers.

Asynchronous circuits.

Logic circuits.

Pulse circuits.

Physical Description:

xxv, 206 pages : illustrations ; 25 cm

Place of Publication:

Boston : Kluwer Academic Publishers, [2002]

Summary:

Asynchronous Pulse Logic is a comprehensive analysis of a newly developed asynchronous circuit family. The book covers circuit theory, practical circuits, design tools and an example of the design of a simple asynchronous microprocessor using the circuit family. Asynchronous Pulse Logic will be of interest to industrial and academic researcher working on high-speed VLSI systems. Graduate students will find this useful reference for computer-aided design of asynchronous or related VLSI systems.

Contents:

1 High-speed CMOS-circuits 1

2 Asynchronous protocols and delay-insensitive codes 3

3 Production rules 4

4 The MiniMIPS processor 4

5 Commonly used abbreviations 6

2. Asynchronous-Pulse-Logic Basics 7

2 The pulse repeater 10

2.1 Timing constraints in the pulse repeater 11

2.2 Simulating the pulse repeater 11

2.3 The synchronous digital model 18

2.4 Asymmetric pulse-repeaters 20

3 Formal model of pulse repeater 21

3.2 Handling the practical simulations 22

3.3 Expanding the model 24

3.4 Using the extended model 26

3.5 Noise margins 28

4 Differential-equations treatment of pulse repeater 29

4.1 Input behavior of pulse repeater 30

4.2 Generalizations and restrictions 34

3. Computing with Pulses 37

1 A simple logic example 38

2 Pulse-handshake duty-cycle 42

3 Single-track-handshake interfaces 45

4 Timing constraints and timing "assumptions" 46

5 Minimum cycle-transition-counts 47

6 Solutions to transition-count problem 48

7 The APL design-style in short 48

4. A Single-Track Asynchronous-Pulse-Logic Family: I. Basic Circuits 51

1.1 Transition counting in pipelined asynchronous circuits 52

1.2 Transition-count choices in pulsed circuits 53

1.3 Execution model 56

1.4 Capabilities of the STAPL family 56

1.5 Design philosophy 58

2 The basic template 58

2.1 Bit generator 59

2.2 Bit bucket 63

2.3 Left-right buffer 66

3 Summary of properties of the simple circuits 71

5. A Single-Track Asynchronous-Pulse-Logic Family: II. Advanced Circuits 73

1 Multiple input and output channels 73

1.1 Naive implementation 74

1.2 Double triggering of logic block in the naive design 75

1.3 Solution 76

1.4 Timing assumptions 77

2 General logic computations 77

2.1 Inputs whose values are not used 78

3 Conditional communications 81

3.1 The same program can be expressed in several ways 83

3.2 Simple techniques for sends 83

3.3 General techniques for conditional communications 84

4 Storing state 89

4.1 The general state-storing problem 89

4.2 Implementing state variables 90

4.3 Compiling the state bit 92

5 Special circuits 95

5.1 Arbitration 96

5.2 Four-phase converters 99

6 Resetting STAPL circuits 100

6.1 Previously used resetting schemes 101

6.3 Generating initial tokens 104

7 How our circuits relate to the design philosophy 105

8 Noise 106

8.1 External noise-sources 106

8.2 Charge sharing 107

8.3 Crosstalk 107

8.4 Design inaccuracies 109

6. Automatic Generation of Asynchronous-Pulse-Logic Circuits 111

1 Straightforwardly compiling from a higher-level specification 111

2 An alternative compilation method 113

3 What we compile 113

4 The PL1 language 114

4.1 Channels or shared variables? 115

4.2 Simple description of the PL1 language 115

4.3 An example: the replicator 117

5 Compiling PL1 118

6 PL1-compiler front-end 120

6.1 Determinism conditions 120

6.2 Data encoding 122

7 PL1-compiler back-end 124

7.1 Slack 125

7.2 Logic simplification 127

7.3 Code generation 129

7. A Design Example: The Spam Microprocessor 133

1 The SPAM architecture 133

2 SPAM implementation 134

2.1 Decomposition 134

2.2 Arbitrated branch-delay 136

2.3 Byte skewing 137

3 Design examples 140

3.1 The PCUNIT 140

3.2 The REGFILE 151

4 Performance measurements on the SPAM implementation 158

4.1 Straightline program 158

4.2 Computing Fibonacci numbers 160

4.3 Energy measurements 162

4.4 Summary of SPAM implementation's performance 163

4.5 Comparison with QDI 163

1 Theory 167

2 STAPL circuit family 167

3 PL1 language 169

4 SPAM microprocessor 170

PL1 Report 173

0.1 Scope 173

0.2 Structure of PL1 173

1 Syntax elements 174

1.1 Keywords 174

1.2 Comments 174

1.3 Numericals 174

1.4 Identifiers 174

1.5 Reserved special operators 174

1.6 Expression operators 174

1.7 Expression syntax 175

1.8 Actions 175

2 PL1 process description 176

2.1 Declarations 176

2.2 Communication statement 176

2.3 Process communication-block 176

3 Semantics 178

3.1 Expression semantics 178

3.2 Action semantics 180

3.3 Execution semantics 180

3.4 Invariants 181

3.5 Semantics in terms of CHP 181

3.6 Slack elasticity 183

SPAM Processor Architecture Definition 187

1 SPAM overview 187

2 SPAM instruction format 187

3 SPAM instruction semantics 189

3.1 Operand generation 189

3.2 Operation definitions 189

4 Assembly-language conventions 191

4.1 The SPAM assembly format 191

Proof that Definition 2.2 Defines a Partial Order 193

1 Remark on Continuity 194.

Notes:

Includes bibliographical references (pages [195]-200) and index.

ISBN:

1402070683

OCLC:

49493444