A computer-aided design and synthesis environment for analog integrated circuits / Geert van der Plas, Georges Gielen, and Willy Sansen.

Format:

Book

Author/Creator:

Van der Plas, Geert.

Contributor:

Gielen, Georges.

Sansen, Willy M. C.

Series:

Kluwer international series in engineering and computer science ; SECS 672.

Kluwer international series in engineering and computer science. Analog circuits and signal processing

The Kluwer international series in engineering and computer science ; SECS 672. Analog circuits and signal processing

Language:

English

Subjects (All):

Linear integrated circuits--Computer-aided design.

Linear integrated circuits.

Integrated circuits--Computer-aided design.

Integrated circuits.

Physical Description:

xvi, 211 pages : illustrations ; 25 cm.

Place of Publication:

Boston : Kluwer Academic Publishers, [2002]

Contents:

I Automatic Synthesis of Analog Circuits 13

2 The AMGIE Analog Synthesis System 15

2.3 Overview of Analog Synthesis Research 19

2.3.1 Early Work 20

2.3.2 Second Generation 21

2.3.3 Most Recent Work 23

2.4 The AMGIE Synthesis System 26

2.4.1 Functionality of the Analog Synthesis Environment 26

2.4.2 Software Architecture of the AMGIE System 34

3 Detailed Description of the AMGIE Analog Synthesis System 39

3.1 Specifications and Hierarchy 39

3.2 Topology Selection Tool 42

3.2.1 Boundary Checking Filter 42

3.2.2 Interval Analysis Filter 44

3.2.3 Rule-based Ranking Filter 45

3.3 Sizing and Optimization Tool 45

3.3.1 Sizing Model Generation 47

3.3.2 Circuit Optimization Setup 55

3.4 Layout Generation Tool 61

3.5 Verification Tool 65

3.5.1 Nominal Performance Verification 66

3.5.2 Verification with Mismatches and Technology Spread 69

3.5.3 Verification over Temperature and Power-supply Operating Ranges 70

3.6 Redesign Wizard 70

4 AMGIE Experimental Results 73

4.1 Comparison of Analog Sizing Synthesis: Equation-based vs. Simulation-based 73

4.1.1 Design Specifications 74

4.1.2 Manual Sizing 74

4.1.3 Simulation-based Sizing 75

4.1.4 Equation-based Sizing 76

4.1.5 Comparison & Conclusions 77

4.2 Student Exercise: High-speed Operational Transconductance Amplifier 79

4.2.1 Setup 79

4.2.2 Session 79

4.2.3 Analysis of Results 86

4.3 Charge-Sensitive Amplifier

Pulse-Shaping Amplifier 90

4.3.1 CSA-PSA Specifications 91

4.3.2 CSA-PSA Architecture 92

4.3.3 Topology Selection 101

4.3.4 Sizing Synthesis: OPTIMAN 102

4.3.5 Layout Generation 102

4.3.6 Verification 106

4.3.7 Measurement Results 106

II Systematic Design of Analog Circuits 113

5 Mondriaan: a Layout Synthesis Methodology for Array-type Analog Blocks 117

5.1 Requirements of the New Layout Generation Methodology 119

5.2 Description of the Layout Model 120

5.3 Description of the Layout Generation Methodology 123

5.3.1 Floorplanning 124

5.3.2 Symbolic Routing 125

5.3.3 Technology Mapping 126

5.3.4 Bus and Tree Generators 127

5.4 Illustrative Example 130

5.4.1 Current Source Array 130

5.4.2 Switch/Latch Array 133

5.4.3 Assembly 135

5.5 Experimental Results 137

5.5.1 Folding/Interpolating A/D-converter Modules 137

5.5.2 Current-Steering D/A-converter Modules 140

6 Systematic Design of Current-Steering D/A-converters 145

6.1 Functionblock Design Flow 146

6.2 Current-Steering D/A-converter Architecture 148

6.2.1 Operating Principle and Specifications 148

6.2.2 Proposed Architecture and its Design Parameters 149

6.3 Behavioral Modeling for the Specification Phase 152

6.3.1 Dynamic Behavior 152

6.3.2 Static Behavior 154

6.4 Synthesis Flow of the D/A-converter 154

6.5 Sizing Synthesis 156

6.5.1 Architectural-level Synthesis 156

6.5.2 Circuit-level Synthesis 159

6.5.3 Full Decoder Synthesis 161

6.5.4 Clock Driver Synthesis 163

6.6 Layout Generation 163

6.6.1 Floorplanning 163

6.6.2 Current Source Array Layout Generation 164

6.6.3 Swatch Array Layout Generation 176

6.6.4 Full Decoder Standard Cell Place and Route 177

6.6.5 Layout Assembly 177

6.7 Extraction of a Behavioral Model for Verification 178

6.7.1 Static Behavior: INL 178

6.7.2 Dynamic Behavior: Glitch Energy 179

6.8 Experimental Results 181

6.8.1 Measurement Setup 181

6.8.2 Measurement Results 182

6.8.3 Breakdown of Design Time 184.

Notes:

Includes bibliographical references (pages [193]-204) and index.

ISBN:

0792376978

OCLC:

49859910