Silicon wafer bonding technology : for VLSI and MEMS applications / edited by Subramanian S. Iyer and Andre J. Auberton-Hervé.

Format:

Book

Contributor:

Iyer, Subramanian S.

Auberton-Hervé, Andre J.

Institution of Electrical Engineers.

INSPEC (Information service). EMIS Group.

Series:

EMIS processing series ; no. 1.

EMIS processing series ; no. 1

Language:

English

Subjects (All):

Silicon-on-insulator technology.

Integrated circuits--Very large scale integration.

Integrated circuits.

Microelectromechanical systems.

Physical Description:

xxv, 149 pages : illustrations ; 26 cm.

Place of Publication:

London : Institution of Electrical Engineers, [2002]

Contents:

1 Principles of wafer bonding / Q.-Y. Tong 1

1.2 Wafer Bonding Basics 3

1.2.1 Surface smoothness 3

1.2.2 Surface flatness 5

1.2.3 Surface cleanliness 7

1.2.4 Standard wafer bonding and layer transfer procedures 7

1.3 Generic Nature of Wafer Bonding 13

1.4 Low Temperature Wafer Bonding 13

1.4.2 Room temperature covalent bonding 14

1.4.3 Low temperature epitaxial wafer bonding 16

2 Bond, grind-back and polish SOI / K. Mitani 21

2.2 Processing 21

2.2.1 Fabrication process flow 21

2.2.2 Initial bonding 22

2.2.3 Bonding anneal 24

2.2.4 Thinning by grinding and polishing 25

2.2.5 Thinning by PACE 29

2.2.6 Wafer size availability 30

2.3 Physical and Electrical Properties 30

2.3.1 Warpage and stress 30

2.3.2 Crystal defects 31

2.3.3 Fixed charges in BOX 33

3 Smart Cut: the technology used for high volume SOI wafer production / B. Aspar, A.J. Auberton-Herve 35

3.2 Processing 35

3.3 Physical Mechanisms 36

3.3.1 Effect of hydrogen implantation in silicon 36

3.3.2 Splitting kinetics 41

3.3.3 Cleaning and bonding 43

3.4 Applications 44

3.4.2 Silicon on insulator wafers 44

3.4.3 Transfer of thin semiconductor films on new bonded layers 46

3.4.4 Transfer of materials other than silicon 48

4 ELTRAN (SOI-Epi wafer) technology / T. Yonehara 53

4.2 Special Features of ELTRAN 53

4.2.1 SOI-Epi wafer 53

4.2.2 Surface smoothing techniques 54

4.2.3 Film thickness control 56

4.2.4 Cloning (wafer recycling) 56

4.3 Processing 56

4.3.2 Anodization 57

4.3.3 Epitaxial growth 58

4.3.4 Bonding and splitting 59

4.3.5 Etching 60

4.3.6 Hydrogen annealing 62

4.4 Applicability and Comparisons 63

4.4.1 SOI/BOX thickness requirement for various SOI device applications 63

4.4.2 Ultra thin SOI 64

4.4.3 Comparisons 67

4.5 Cost Reduction and Scalability 70

4.5.2 Recycling of seed wafer 70

4.5.3 Double porous Si layers 72

4.5.4 Splitting with a water jet 74

4.5.5 300 mm wafer SOI 77

5 Wafer characterization / G. Pfeiffer, S.S. Iyer 83

5.2 Characterization Techniques 84

5.2.1 Bonding strength/layer integrity 84

5.2.2 Layer thickness measurements 85

5.2.3 Surface characterization 86

5.2.4 Contamination/doping 87

5.2.5 Defect decoration 88

5.2.6 Pseudo MOSFET 88

5.2.7 BOX measurements 90

6 Advanced applications of wafer bonding / E.C. Jones, S.W. Bedell 93

6.2 Advanced Microelectronics 93

6.2.1 High performance partially depleted and fully depleted CMOS 93

6.2.2 Double gate CMOS 95

6.2.3 3D device integration 98

6.3 Photonics and Optoelectronics 102

6.3.2 Light sources 102

6.3.3 Light detectors 104

6.3.4 Waveguides and couplers 105

6.3.5 Switches, modulators and other structures 107

6.4 Compliant Substrates 108

6.4.2 Thin SOI and glass-bonded compliant substrates 109

6.4.3 Twist bonded compliant substrates 111

6.5 Microelectromechanical Systems (MEMS) 113

6.5.2 MEMS background 114

6.5.3 Wafer bonding as an enabling technology for MEMS 115

6.6 Monolithic Integration 117

Appendix 1 A manufacturing process for silicon-on-silicon wafer bonding / I.K. Bansal, J.P. Goodrich 123

A1.2 Direct Wafer Bonding 123

A1.2.1 Surface preparation 124

A1.2.2 Contacting 124

A1.2.3 Thermal annealing 125

A1.3 Physical Parameters of Incoming Silicon Substrates 125

A1.4 Pre-join Surface Preparation 126

A1.5 Ambient Temperature Bonding 127

A1.6 Thermal Annealing Process 128

A1.7 Analysis of Voids Within the Thermally Annealed Interface 128

A1.8 Grinding of Device Layer to Semi-Finished Thickness 129

A1.9 Measurement of Carrier Concentration Across the Interface Layer 129

A1.10 Data and Results 129

A1.10.1 Non-megasonic 'concentrated' RCA clean plus single-side-scrub (SSS) 130

A1.10.2 Megasonic 'very dilute' RCA clean plus Marangoni drying 131

A1.10.3 SRP analysis of bonded interface layer 133

A1.11 Semiconductor Applications 133

Appendix 3 Comparison of bonded wafer technologies 141.

Notes:

Includes bibliographical references and index.

ISBN:

0852960395

OCLC:

48026089