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Verilog-2001 : a guide to the new features of the Verilog hardware description language / Stuart Sutherland.
LIBRA TK7885.7 .S878 2002
Available from offsite location
- Format:
- Book
- Author/Creator:
- Sutherland, Stuart, 1953-
- Series:
- Kluwer international series in engineering and computer science
- Language:
- English
- Subjects (All):
- Verilog (Computer hardware description language).
- Electronic digital computers--Design and construction--Data processing.
- Electronic digital computers.
- Physical Description:
- 135 pages : illustrations ; 24 cm.
- Place of Publication:
- Boston : Kluwer Academic, [2002]
- Summary:
- The IEEE 1364-2001 standard, nicknamed Verilog-2001', is thefirst major update to the Verilog language since its inception in1984. This book presents 45 significant enhancements contained inVerilog-2001 standard. A few of the new features described in thisbook are: This book assumes that the reader is already familiar with usingVerilog. It supplements other excellent books on how to use theVerilog language, such as "The Verilog Hardware DescriptionLanguage," by Donald Thomas and Philip Moorby (Kluwer AcademicPublishers, ISBN: 0-7923-8166-1) and "Verilog Quickstart: APractical Guide to Simulation" "and Synthesis," by James Lee(Kluwer Academic Publishers, ISBN: 0-7923-8515-2).
- Contents:
- 1. Combined port and data type declarations 8
- 2. ANSI C style module declarations 10
- 3. Module port parameter lists 12
- 4. ANSI C style UDP declarations 14
- 5. Variable initial value at declaration 16
- 6. ANSI C style task/function declarations 18
- 7. Automatic (re-entrant) tasks 20
- 8. Automatic (recursive) functions 22
- 9. Constant functions 24
- 10. Comma separated sensitivity lists 26
- 11. Combinational logic sensitivity lists 28
- 12. Implicit nets for continuous assignments 32
- 13. Disabling implicit net declarations 34
- 14. Variable vector part selects 36
- 15. Multidimensional arrays 38
- 16. Arrays of net and real data types 40
- 17. Array bit and part selects 41
- 18. Signed reg, net and port declarations 42
- 19. Signed based integer numbers 44
- 20. Signed functions 46
- 21. Sign conversion system functions 48
- 22. Arithmetic shift operators 50
- 23. Assignment width extension past 32 bits 52
- 24. Power operator 54
- 25. Attributes 56
- 26. Sized and typed parameter constants 59
- 27. Explicit in-line parameter redefinition 62
- 28. Fixed local parameters 64
- 29. Standard random number generator 66
- 30. Extended number of open files 67
- 31. Enhanced file I/O 70
- 32. String read and write system tasks 76
- 33. Enhanced invocation option testing 78
- 34. Enhanced conditional compilation 80
- 35. Source file and line compiler directive 82
- 36. Generate blocks 84
- 37. Configurations 90
- 38. On-detect pulse error propagation 94
- 39. Negative pulse detection 96
- 40. Enhanced input timing checks 98
- 41. Negative input timing constraints 100
- 42. Enhanced SDF file support 102
- 43. Extended VCD files 104
- 44. Enhanced PLA system tasks 106
- 45. Enhanced Verilog PLI support 107
- Appendix A Verilog-2001 formal definition 109
- Appendix B Verilog-2001 reserved words 131.
- Notes:
- Includes index.
- ISBN:
- 0792375688
- OCLC:
- 48858499
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