Scanning probe lithography / by Hyongsok T. Soh, Kathryn Wilder Guarini, Calvin F. Quate.

Format:

Book

Author/Creator:

Soh, H. Tom.

Contributor:

Guarini, Kathryn Wilder.

Quate, Calvin F., 1923-2019.

Series:

Microsystems (Series) ; 7.

Microsystems ; 7

Language:

English

Subjects (All):

Integrated circuits--Design and construction.

Integrated circuits.

Microlithography.

Scanning probe microscopy.

Physical Description:

xxiii, 195 pages : illustrations ; 25 cm.

Place of Publication:

Boston : Kluwer Academic Publishers, [2001]

Contents:

1.1 The Scanning Probe Microscope 1

1.1.1 The Scanning Tunneling Microscope 2

1.1.2 The Atomic Force Microscope 3

1.1.3 Innovations Through Integration 4

1.2 High-Resolution Patterning Using Scanning Probes 6

1.2.2 Mechanical & Thermomechanical Patterning 7

1.2.3 Local Oxidation 8

1.2.4 Electron Exposure of Resist 9

1.3 Semiconductor Lithography 9

Chapter 2 SPL by Electric-Field-Enhanced Oxidation 23

2.1 Field-Enhanced Oxidation of Silicon 23

2.2 Amorphous Silicon as a Resist Material 24

2.3 Fabrication of a 100 nm nMOSFET 26

Chapter 3 Resist Exposure Using Field-Emitted Electrons 37

3.1 Field-Emitted Electron Exposure 37

3.2 Current-Controlled Exposures in Contact Mode 48

3.3 Current-Controlled Exposures in Noncontact Mode 60

3.3.2 Patterning in the Noncontact Mode 62

3.3.3 Line Width Control 65

3.3.4 Comparison of Contact and Noncontact Mode Results 66

3.3.5 Summary of Noncontact Mode SPL 67

3.4 Simulations of Electron Field Emission and Electron Trajectories 67

3.4.1 Initial Beam Size in the Contact Configuration 68

3.4.2 Comparison of Contact and Noncontact Configurations 71

3.4.3 Beam Spreading 75

3.4.4 Summary of Simulation Results 75

Chapter 4 SPL Linewidth Control 81

4.1 Exposure Tools and Samples 81

4.2 Sensitivity and Exposure Latitude 84

4.3 Energy Density Distribution in the Resist 85

4.4 Patterning Linearity Using a Pixel Writing Scheme 88

4.5 Proximity Effects 91

4.6 Exposure Mechanisms of High- and Low-Energy Electrons 97

Chapter 5 Critical Dimension Patterning Using SPL 103

5.1 100 nm pMOSFET Device Fabrication 103

5.2 Gate Level Lithography Using SPL 105

5.2.1 Overlay Registration 106

5.2.2 Patterning Over Topography 106

5.3 PMOSFET Device Characteristics 110

5.4 Summary of "Mix and Match" Lithography 112

Chapter 6 High Speed Resist Exposure With a Single Tip 115

6.1 High Speed Patterning of Siloxane SOG 115

6.1.1 Mechanism of Exposure 115

6.1.2 Experimental Procedure 117

6.1.3 Results of SOG Patterning 118

6.2 Current-Controlled SPL at High Speeds 119

6.2.1 Control of the Tip-Sample Force or Spacing at High Speeds 120

6.2.2 Control of the Emission Current at High Speeds 121

6.2.3 High Speed Lithography 125

6.2.4 Summary of High Speed SPL Using a Single Tip 126

Chapter 7 On-Chip Lithography Control 131

7.1 Background and Motivation 131

7.2 MOSFET Design Considerations 132

7.2.1 Saturation Current 134

7.2.2 Threshold Voltage 134

7.2.3 Junction Breakdown 135

7.2.4 Off Current 136

7.2.5 Switching Speed 137

7.3 Cantilever and Tip Design Parameters 138

7.4 Fabrication Process 140

7.4.1 Tip Formation and Cantilever Definition 142

7.4.2 Front-End Transistor Fabrication 143

7.4.3 Back-End Transistor Fabrication 144

7.4.4 Cantilever Release 144

7.5 Device Characteristics 146

7.6 Lithography with Integrated Transistor for Exposure Dose Control 148

Chapter 8 Scanning Probe Tips for SPL 153

8.1 Silicon and Metal-Coated Tips 153

8.2 Post-Processed Silicon Tips 155

8.3 Carbon Nanotubes as Scanning Probe Tips 156

8.3.1 Direct Synthesis on Silicon Pyramidal Tips 157

Chapter 9 Scanning Probe Arrays for Lithography 163

9.1 Current-Controlled Lithography With Two Tips 163

9.1.1 High-Voltage Current Preamplifier 164

9.1.2 Independent Parallel Lithography 166

9.1.3 Summary of Progress on Parallel Lithography 167

9.2 Massively Parallel Arrays for Lithography 167

9.2.1 Exposure Time for Different Size Arrays 168

9.2.2 SPL Throughput Using Cantilever Arrays 170

9.3 Integrated Current Control for Arrays 172

9.4 Two Dimensional Arrays: Process Development 173

9.4.1 Enabling Technologies 173

9.4.2 Anisotropic Through Wafer Etching 174

9.4.3 Through-Wafer Via Process 175

9.5 Two Dimensional Arrays: Integration 178

9.5.1 Introduction to the Piezoresistive Cantilever 178

9.5.2 Design and Modeling 178

9.5.3 Processing 181

9.6 Imaging With the 2D Array 187.

Notes:

Includes bibliographical references and index.

ISBN:

0792373618

OCLC:

46866288