Digital design : principles and practices / John F. Wakerly.

Format:

Book

Author/Creator:

Wakerly, John F.

Contributor:

Alumni and Friends Memorial Book Fund.

Language:

English

Subjects (All):

Digital integrated circuits--Design and construction.

Digital integrated circuits.

Physical Description:

xxiii, 946 pages : illustrations ; 25 cm + 2 computer optical discs (4 3/4 in.)

4 3/4 in.

Edition:

Third edition.

Other Title:

Title on discs : Foundation series software Version 1.5 : XILINX student version

Place of Publication:

Upper Saddle River, N.J. : Prentice Hall, [2000]

System Details:

System requirements: Pentium processor recommended; Windows 95 or NT 4.0; 48MB RAM recommended; 350MB (plus 100MB swap space) free hard drive space.

text file

Summary:

This newly revised book blends academic precision and practical experience in an authoritative introduction to basic principles of digital design and practical requirements in both board-level and VLSI systems. With over twenty years of experience in both university and industrial settings, John Wakerly has directly taught thousands of engineering students, indirectly taught tens of thousands through his books, and directly designed real digital systems representing tens of millions of dollars of revenue.

The book covers the fundamental building blocks of digital design across several levels of abstraction, from CMOS gates to hardware design languages. Important functions such as gates, decoders, multiplexers, flip-flops, registers, and counters are discussed at each level.

New edition features include de-emphasis of manual turn-the-crank procedures and MSI design, and earlier coverage of PLDs, FPGAs, and hardware design languages to get maximum leverage from modern components and software tools. HDL coverage now includes VHDL as well as ABEL.

Contents:

1.1 About Digital Design 1

1.2 Analog versus Digital 3

1.3 Digital Devices 6

1.4 Electronic Aspects of Digital Design 7

1.5 Software Aspects of Digital Design 9

1.6 Integrated Circuits 12

1.7 Programmable Logic Devices 15

1.8 Application-Specific ICs 16

1.9 Printed-Circuit Boards 18

1.10 Digital-Design Levels 18

1.11 The Name of the Game 22

1.12 Going Forward 23

2 Number Systems and Codes 25

2.1 Positional Number Systems 26

2.2 Octal and Hexadecimal Numbers 27

2.3 General Positional-Number-System Conversions 29

2.4 Addition and Subtraction of Nondecimal Numbers 32

2.5 Representation of Negative Numbers 34

2.5.1 Signed-Magnitude Representation

2.5.2 Complement Number Systems

2.5.3 Radix-Complement Representation

2.5.4 Two's-Complement Representation

2.5.5 Diminished Radix-Complement Representation

2.5.6 Ones'-Complement Representation

2.5.7 Excess Representations

2.6 Two's-Complement Addition and Subtraction 39

2.6.1 Addition Rules

2.6.2 A Graphical View

2.6.3 Overflow

2.6.4 Subtraction Rules

2.6.5 Two's-Complement and Unsigned Binary Numbers

2.7 Ones'-Complement Addition and Subtraction 44

2.8 Binary Multiplication 45

2.9 Binary Division 47

2.10 Binary Codes for Decimal Numbers 48

2.11 Gray Code 51

2.12 Character Codes 53

2.13 Codes for Actions, Conditions, and States 53

2.14 n-Cubes and Distance 57

2.15 Codes for Detecting and Correcting Errors 58

2.15.1 Error-Detecting Codes

2.15.2 Error-Correcting and Multiple-Error-Detecting Codes

2.15.3 Hamming Codes

2.15.4 CRC Codes

2.15.5 Two-Dimensional Codes

2.15.6 Checksum Codes

2.15.7 m-out-of-n Codes

2.16 Codes for Serial Data Transmission and Storage 69

2.16.1 Parallel and Serial Data

2.16.2 Serial Line Codes

3 Digital Circuits 79

3.1 Logic Signals and Gates 80

3.2 Logic Families 84

3.3 CMOS Logic 86

3.3.1 CMOS Logic Levels

3.3.2 MOS Transistors

3.3.3 Basic CMOS Inverter Circuit

3.3.4 CMOS NAND and NOR Gates

3.3.5 Fan-In

3.3.6 Noninverting Gates

3.3.7 CMOS AND-OR-INVERT and OR-AND-INVERT Gates

3.4 Electrical Behavior of CMOS Circuits 96

3.4.2 Data Sheets and Specifications

3.5 CMOS Steady-State Electrical Behavior 99

3.5.1 Logic Levels and Noise Margins

3.5.2 Circuit Behavior with Resistive Loads

3.5.3 Circuit Behavior with Nonideal Inputs

3.5.4 Fanout

3.5.5 Effects of Loading

3.5.6 Unused Inputs

3.5.7 Current Spikes and Decoupling Capacitors

3.5.8 How to Destroy a CMOS Device

3.6 CMOS Dynamic Electrical Behavior 113

3.6.1 Transition Time

3.6.2 Propagation Delay

3.6.3 Power Consumption

3.7 Other CMOS Input and Output Structures 123

3.7.1 Transmission Gates

3.7.2 Schmitt-Trigger Inputs

3.7.3 Three-State Outputs

3.7.4 Open-Drain Outputs

3.7.5 Driving LEDs

3.7.6 Multisource Buses

3.7.7 Wired Logic

3.7.8 Pull-Up Resistors

3.8 CMOS Logic Families 135

3.8.1 HC and HCT

3.8.2 VHC and VHCT

3.8.3 HC, HCT, VHC, and VHCT Electrical Characteristics

3.8.4 FCT and FCT-T

3.8.5 FCT-T Electrical Characteristics

3.9 Bipolar Logic 145

3.9.1 Diodes

3.9.2 Diode Logic

3.9.3 Bipolar Junction Transistors

3.9.4 Transistor Logic Inverter

3.9.5 Schottky Transistors

3.10 Transistor-Transistor Logic 156

3.10.1 Basic TTL NAND Gate

3.10.2 Logic Levels and Noise Margins

3.10.3 Fanout

3.10.4 Unused Inputs

3.10.5 Additional TTL Gate Types

3.11 TTL Families 166

3.11.1 Early TTL Families

3.11.2 Schottky TTL Families

3.11.3 Characteristics of TTL Families

3.11.4 A TTL Data Sheet

3.12 CMOS/TTL Interfacing 170

3.13 Low-Voltage CMOS Logic and Interfacing 171

3.13.1 3.3-V LVTTL and LVCMOS Logic

3.13.2 5-V Tolerant Inputs

3.13.3 5-V Tolerant Outputs

3.13.4 TTL/LVTTL Interfacing Summary

3.13.5 2.5-V and 1.8-V Logic

3.14 Emitter-Coupled Logic 175

3.14.1 Basic CML Circuit

3.14.2 ECL 10K/10H Families

3.14.3 ECL 100K Family

3.14.4 Positive ECL (PECL)

4 Combinational Logic Design Principles 193

4.1 Switching Algebra 194

4.1.1 Axioms

4.1.2 Single-Variable Theorems

4.1.3 Two- and Three-Variable Theorems

4.1.4 n-Variable Theorems

4.1.5 Duality

4.1.6 Standard Representations of Logic Functions

4.2 Combinational-Circuit Analysis 209

4.3 Combinational-Circuit Synthesis 215

4.3.1 Circuit Descriptions and Designs

4.3.2 Circuit Manipulations

4.3.3 Combinational-Circuit Minimization

4.3.4 Karnaugh Maps

4.3.5 Minimizing Sums of Products

4.3.6 Simplifying Products of Sums

4.3.7 "Don't-Care" Input Combinations

4.3.8 Multiple-Output Minimization

4.4 Programmed Minimization Methods 236

4.4.1 Representation of Product Terms

4.4.2 Finding Prime Implicants by Combining Product Terms

4.4.3 Finding a Minimal Cover Using a Prime-Implicant Table

4.4.4 Other Minimization Methods

4.5 Timing Hazards 244

4.5.1 Static Hazards

4.5.2 Finding Static Hazards Using Maps

4.5.3 Dynamic Hazards

4.5.4 Designing Hazard-Free Circuits

4.6 The ABEL Hardware Description Language 249

4.6.1 ABEL Program Structure

4.6.2 ABEL Compiler Operation

4.6.3 WHEN Statements and Equation Blocks

4.6.4 Truth Tables

4.6.5 Ranges, Sets, and Relations

4.6.6 Don't-Care Inputs

4.6.7 Test Vectors

4.7 The VHDL Hardware Description Language 264

4.7.1 Design Flow

4.7.2 Program Structure

4.7.3 Types and Constants

4.7.4 Functions and Procedures

4.7.5 Libraries and Packages

4.7.6 Structural Design Elements

4.7.7 Dataflow Design Elements

4.7.8 Behavioral Design Elements

4.7.9 The Time Dimension and Simulation

4.7.10 Synthesis

5 Combinational Logic Design Practices 311

5.1 Documentation Standards 312

5.1.1 Block Diagrams

5.1.2 Gate Symbols

5.1.3 Signal Names and Active Levels

5.1.4 Active Levels for Pins

5.1.5 Bubble-to-Bubble Logic Design

5.1.6 Drawing Layout

5.1.7 Buses

5.1.8 Additional Schematic Information

5.2 Circuit Timing 330

5.2.1 Timing Diagrams

5.2.2 Propagation Delay

5.2.3 Timing Specifications

5.2.4 Timing Analysis

5.2.5 Timing Analysis Tools

5.3 Combinational PLDs 337

5.3.1 Programmable Logic Arrays

5.3.2 Programmable Array Logic Devices

5.3.3 Generic Array Logic Devices

5.3.4 Bipolar PLD Circuits

5.3.5 CMOS PLD Circuits

5.3.6 Device Programming and Testing

5.4 Decoders 351

5.4.1 Binary Decoders

5.4.2 Logic Symbols for Larger-Scale Elements

5.4.3 The 74[times]139 Dual 2-to-4 Decoder

5.4.4 The 74[times]138 3-to-8 Decoder

5.4.5 Cascading Binary Decoders

5.4.6 Decoders in ABEL and PLDs

5.4.7 Decoders in VHDL

5.4.8 Seven-Segment Decoders

5.5 Encoders 376

5.5.1 Priority Encoders

5.5.2 The 74[times]148 Priority Encoder

5.5.3 Encoders in ABEL and PLDs

5.5.4 Encoders in VHDL

5.6 Three-State Devices 385

5.6.1 Three-State Buffers

5.6.2 Standard SSI and MSI Three-State Buffers

5.6.3 Three-State Outputs in ABEL and PLDs

5.6.4 Three-State Outputs in VHDL

5.7 Multiplexers 398

5.7.1 Standard MSI Multiplexers

5.7.2 Expanding Multiplexers

5.7.3 Multiplexers, Demultiplexers, and Buses

5.7.4 Multiplexers in ABEL and PLDs

5.7.5 Multiplexers in VHDL

5.8 Exclusive-OR Gates and Parity Circuits 410

5.8.1 Exclusive-OR and Exclusive-NOR Gates

5.8.2 Parity Circuits

5.8.3 The 74x280 9-Bit Parity Generator

5.8.4 Parity-Checking Applications

5.8.5 Exclusive-OR Gates and Parity Circuits in ABEL and PLDs

5.8.6 Exclusive-OR Gates and Parity Circuits in VHDL

5.9 Comparators 419

5.9.1 Comparator Structure

5.9.2 Iterative Circuits

5.9.3 An Iterative Comparator Circuit

5.9.4 Standard MSI Comparators

5.9.5 Comparators in ABEL and PLDs

5.9.6 Comparators in VHDL

5.10 Adders, Subtractors, and ALUs 430

5.10.1 Half Adders and Full Adders

5.10.2 Ripple Adders

5.10.3 Subtractors

5.10.4 Carry Lookahead Adders

5.10.5 MSI Adders

5.10.6 MSI Arithmetic and Logic Units

5.10.7 Group-Carry Lookahead

5.10.8 Adders in ABEL and PLDs

5.10.9 Adders in VHDL

5.11 Combinational Multipliers 446

5.11.1 Combinational Multiplier Structures

5.11.2 Multiplication in ABEL and PLDs

5.11.3 Multiplication in VHDL

6 Combinational-Circuit Design Examples 467

6.1 Building-Block Design Examples 468

6.1.1 Barrel Shifter

6.1.2 Simple Floating-Point Encoder

6.1.3 Dual-Priority Encoder

6.1.4 Cascading Comparators

6.1.5 Mode-Dependent Comparator

6.2 Design Examples Using ABEL and PLDs 479

6.2.1 Barrel Shifter

6.2.2 Simple Floating-Point Encoder

6.2.3 Dual-Priority Encoder

6.2.4 Cascading Comparators

6.2.5 Mode-Dependent Comparator

6.2.6 Ones Counter

6.2.7 Tic-Tac-Toe

6.3 Design Examples Using VHDL 500

6.3.1 Barrel Shifter

6.3.2 Simple Floating-Point Encoder

6.3.3 Dual-Priority Encoder

6.3.4 Cascading Comparators

6.3.5 Mode-Dependent Comparator

6.3.6 Ones Counter

6.3.7 Tic-Tac-Toe

7 Sequential Logic Design Principles 529

7.1 Bistable Elements 531

7.1.1 Digital Analysis

7.1.2 Analog Analysis

7.1.3 Metastable Behavior

7.2 Latches and Flip-Flops 534

7.2.1 S-R Latch

7.2.2 S-R Latch

7.2.3 S-R Latch with Enable

7.2.4 D Latch

7.2.5 Edge-Triggered D Flip-Flop

7.2.6 Edge-Triggered D Flip-Flop with Enable

7.2.7 Scan Flip-Flop

7.2.8 Master/Slave S-R Flip-Flop

7.2.9 Master/Slave J-K Flip-Flop

7.2.10 Edge-Triggered J-K Flip-Flop

7.2.11 T Flip-Flop

7.3 Clocked Synchronous State-Machine Analysis 550

7.3.1 State-Machine Structure

7.3.2 Output Logic

7.3.3 Characteristic Equations

7.3.4 Analysis of State Machines with D Flip-Flops

7.3.5 Analysis of State Machines with J-K Flip-Flops

7.4 Clocked Synchronous State-Machine Design 563

7.4.1 State-Table Design Example

7.4.2 State Minimization

7.4.3 State Assignment

7.4.4 Synthesis Using D Flip-Flops

7.4.5 Synthesis Using J-K Flip-Flops

7.4.6 More Design Examples Using D Flip-Flops

7.5 Designing State Machines Using State Diagrams 584

7.6 State-Machine Synthesis Using Transition Lists 591

7.6.1 Transition Equations

7.6.2 Excitation Equations

7.6.3 Variations on the Scheme

7.6.4 Realizing the State Machine

7.7 Another State-Machine Design Example 594

7.7.1 The Guessing Game

7.7.2 Unused States

7.7.3 Output-Coded State Assignment

7.7.4 "Don't-Care" State Codings

7.8 Decomposing State Machines 602

7.9 Feedback Sequential Circuits 604

7.9.1 Analysis

7.9.2 Analyzing Circuits with Multiple Feedback Loops

7.9.3 Races

7.9.4 State Tables and Flow Tables

7.9.5 CMOS D Flip-Flop Analysis

7.10 Feedback Sequential-Circuit Design 615

7.10.1 Latches

7.10.2 Designing Fundamental-Mode Flow Table

7.10.3 Flow-Table Minimization

7.10.4 Race-Free State Assignment

7.10.5 Excitation Equations

7.10.6 Essential Hazards

7.11 ABEL Sequential-Circuit Design Features 627

7.11.1 Registered Outputs

7.11.2 State Diagrams

7.11.3 External State Memory

7.11.4 Specifying Moore Outputs

7.11.5 Specifying Mealy and Pipelined Outputs with With

7.11.6 Test Vectors

7.12 VHDL Sequential-Circuit Design Features 641

7.12.1 Feedback Sequential Circuits

7.12.2 Clocked Circuits

8 Sequential Logic Design Practices 659

8.1 Sequential-Circuit Documentation Standards 660

8.1.1 General Requirements

8.1.2 Logic Symbols

8.1.3 State-Machine Descriptions

8.1.4 Timing Diagrams and Specifications

8.2 Latches and Flip-Flops 666

8.2.1 SSI Latches and Flip-Flops

8.2.2 Switch Debouncing

8.2.3 The Simplest Switch Debouncer

8.2.4 Bus Holder Circuit

8.2.5 Multibit Registers and Latches

8.2.6 Registers and Latches in ABEL and PLDs

8.2.7 Registers and Latches in VHDL

8.3 Sequential PLDs 681

8.3.1 Bipolar Sequential PLDs

8.3.2 Sequential GAL Devices

8.3.3 PLD Timing Specifications

8.4 Counters 693

8.4.1 Ripple Counters

8.4.2 Synchronous Counters

8.4.3 MSI Counters and Applications

8.4.4 Decoding Binary-Counter States

8.4.5 Counters in ABEL and PLDs

8.4.6 Counters in VHDL

8.5 Shift Registers 712

8.5.1 Shift-Register Structure

8.5.2 MSI Shift Registers

8.5.3 The World's Biggest Shift-Register Application

8.5.4 Serial/Parallel Conversion

8.5.5 Shift-Register Counters

8.5.6 Ring Counters

8.5.7 Johnson Counters

8.5.8 Linear Feedback Shift-Register Counters

8.5.9 Shift Registers in ABEL and PLDs

8.5.10 Shift Registers in VHDL

8.6 Iterative versus Sequential Circuits 747

8.7 Synchronous Design Methodology 750

8.7.1 Synchronous System Structure

8.7.2 A Synchronous System Design Example

8.8 Impediments to Synchronous Design 757

8.8.1 Clock Skew

8.8.2 Gating the Clock

8.8.3 Asynchronous Inputs

8.9 Synchronizer Failure and Metastability 764

8.9.1 Synchronizer Failure

8.9.2 Metastability Resolution Time

8.9.3 Reliable Synchronizer Design

8.9.4 Analysis of Metastable Timing

8.9.5 Better Synchronizers

8.9.6 Other Synchronizer Designs

8.9.7 Metastable-Hardened Flip-Flops

8.9.8 Synchronizing High-Speed Data Transfers

9 Sequential-Circuit Design Examples 795

9.1 Design Examples Using ABEL and PLDs 796

9.1.1 Timing and Packaging of PLD-Based State Machines

9.1.2 A Few Simple Machines

9.1.3 T-Bird Tail Lights

9.1.4 The Guessing Game

9.1.5 Reinventing Traffic-Light Controllers

9.2 Design Examples Using VHDL 813

9.2.1 A Few Simple Machines

9.2.2 T-Bird Tail Lights

9.2.3 The Guessing Game

9.2.4 Reinventing Traffic-Light Controllers

10 Memory, Cplds, and Fpgas 831

10.1 Read-Only Memory 832

10.1.1 Using ROMs for "Random" Combinational Logic Functions

10.1.2 Internal ROM Structure

10.1.3 Two-Dimensional Decoding

10.1.4 Commercial ROM Types

10.1.5 ROM Control Inputs and Timing

10.1.6 ROM Applications

10.2 Read/Write Memory 854

10.3 Static RAM 854

10.3.1 Static-RAM Inputs and Outputs

10.3.2 Static-RAM Internal Structure

10.3.3 Static-RAM Timing

10.3.4 Standard Static RAMs

10.3.5 Synchronous SRAM

10.4 Dynamic RAM 866

10.4.1 Dynamic-RAM Structure

10.4.2 Dynamic-RAM Timing

10.4.3 Synchronous DRAMs

10.5 Complex Programmable Logic Devices 872

10.5.1 Xilinx XC9500 CPLD Family

10.5.2 Function-Block Architecture

10.5.3 Input/Output-Block Architecture

10.5.4 Switch Matrix

10.6 Field-Programmable Gate Arrays 882

10.6.1 Xilinx XC4000 FPGA Family

10.6.2 Configurable Logic Block

10.6.3 Input/Output Block

10.6.4 Programmable Interconnect

11 Additional Real-World Topics 895

11.1 Computer-Aided Design Tools 895

11.1.1 Hardware Description Languages

11.1.2 Schematic Capture

11.1.3 Timing Drawings and Specifications

11.1.4 Circuit Analysis and Simulation

11.1.5 PCB Layout

11.2 Design for Testability 902

11.2.1 Testing

11.2.2 Bed-of-Nails and In-Circuit Testing

11.2.3 Scan Methods

11.3 Estimating Digital System Reliability 908

11.3.1 Failure Rates

11.3.2 Reliability and MTBF

11.3.3 System Reliability

11.4 Transmission Lines, Reflections, and Termination 912

11.4.1 Basic Transmission-Line Theory

11.4.2 Logic-Signal Interconnections as Transmission Lines

11.4.3 Logic-Signal Terminations.

Notes:

Includes bibliographical references and index.

Local Notes:

Acquired for the Penn Libraries with assistance from the Alumni and Friends Memorial Book Fund.

ISBN:

0137691912

OCLC:

41592994