The VHDL reference : a practical guide to computer-aided integrated circuit design including VHDL-AMS / Ulrich Heinkel ... [and others].

Format:

Book

Contributor:

Heinkel, Ulrich.

Language:

English

Subjects (All):

VHDL (Computer hardware description language).

Integrated circuits--Design and construction--Data processing.

Integrated circuits.

Physical Description:

xviii, 420 pages : illustrations ; 26 cm + 3 computer optical discs (4 3/4 in.)

4 3/4 in.

Other Title:

Disc 2 title: FPGA Advantage

Disc 3 title: ModelSim : Xilinx edition

Place of Publication:

Chichester ; New York : John Wiley & Sons, 2000.

System Details:

text file

Summary:

Very high-speed integrated circuits Hardware Description Language (VHDL) is the industry standard language for computer-aided electronic system design. This book incorporates a beginners' tutorial, a VHDL reference for engineers together with a workshop featuring design examples.

Contents:

1 VHDL: Overview and Application Field 3

1.1 Application Field of HDLs 3

1.2 Range of Use 6

1.3 VHDL: Overview 7

1.4 Concepts of VHDL 11

2 VHDL Language and Syntax 22

2.2 VHDL Structural Elements 25

2.3 Sequential Statements 50

2.4 Concurrent Statements 62

2.5 Data Types 66

2.6 Extended Data Types 74

2.7 Operators 90

2.8 Subprograms 94

2.9 Subprogram Declaration and Overloading 99

3 Synthesis 104

3.1 What is Synthesis? 104

3.2 RTL Style 110

3.3 Combinational Logic 118

3.4 Sequential Logic 128

3.5 Finite State Machines and VHDL 130

3.6 Advanced Synthesis 149

4 Simulation 154

4.1 Testbenches 154

4.2 Sequence of Compilation 159

4.3 File I/O 161

4.4 Simulation Flow 167

4.5 Process Execution 170

4.6 Delay Models 176

5 Project Management 184

5.1 File Organization 184

5.2 Design Components 184

5.3 Name Spaces 187

5.4 Design Reuse 190

VHDL-AMS Tutorial

6 VHDL-AMS 197

6.2 New VHDL-AMS Language Elements 206

6.3 Modelling 226

VHDL Workshop

1.1 Structure of the Exercises 233

1.2 Style Guide 233

1.3 Design Structure 233

2 VHDL Working Environment 235

2.1 Directory Structure 235

2.2 Working Environment 235

2.3 VHDL Code 236

2.4 VHDL Compiler 237

2.5 VHDL Simulator 237

2.6 VHDL Synthesis 239

3.1 Step 1: A Multiplexer 241

3.2 Step 2: Extending the Multiplexer 243

3.3 Step 3: A 7-Segment Display Driver 245

3.4 Step 4: A Three Digit 7-Segment Display Driver 248

3.5 Step 5: A Decoder 249

3.6 Step 6: A Register 252

3.7 Step 9: A State Machine for the Display 254

3.8 Step 7: A Timer 256

3.9 Step 8: A BCD Counter 258

3.10 Step 9: A State Machine for the Main Controller 262

3.11 Step 10: The Camera 264

1 Design Entities and Configurations 269

1.1 Entity 269

1.2 Architecture 270

1.3 Configuration 272

2 Subprograms and Packages 274

2.1 Subprogram Declaration 274

2.2 Subprogram Body 275

2.3 Overloading 277

2.4 Resolution Function 279

2.5 Package Declaration 280

2.6 Package Body 281

2.7 Conformance Rules 283

3 Types 284

3.1 Scalar Types 284

3.2 Compound Types 285

3.3 Access Types 286

3.4 File Types 287

4 Declarations 288

4.1 Type Declarations 288

4.2 Subtype Declarations 289

4.3 Constant Declarations 291

4.4 Signal Declarations 292

4.5 Variable Declarations 294

4.6 File Declarations 296

4.7 Interface Declarations 298

4.8 Alias Declarations 298

4.9 Attribute Declarations 301

4.10 Component Declarations 302

4.11 Group Template Declarations 303

4.12 Group Declaration 304

5 Specification 306

5.1 Attribute Specification 306

5.2 Configuration Specification 307

5.3 Disconnection Specification 309

6 Names 311

6.2 Simple Names 311

6.3 Selected Names 311

6.4 Indexed Names 312

6.5 Range Names 312

6.6 Attribute Names 313

7 Expressions 314

7.1 Expression 314

7.2 Logic Operators 314

7.3 Relational Operators 315

7.4 Shift Operators 316

7.5 Adding Operators 317

7.6 Multiplying Operators 318

7.7 Miscellaneous Operators 319

7.8 Literals 320

7.9 Aggregates 320

7.10 Function Call 321

7.11 Qualified Expression 321

7.12 Type Conversion 322

7.13 Allocator 322

7.14 Static Expression 323

7.15 Universal Expression 324

8 Sequential Statements 325

8.1 Wait 325

8.2 Assertion 326

8.3 Report 328

8.4 Signal Assignment 329

8.5 Variable Assignment 331

8.6 Procedure Call 332

8.7 If 333

8.8 Case 335

8.9 Loop 336

8.10 Next 338

8.11 Exit 339

8.12 Return 341

8.13 Null 342

9 Concurrent statements 343

9.1 Block 343

9.2 Process 344

9.3 Concurrent Procedure Call 346

9.4 Concurrent Assertion 348

9.5 Concurrent Signal Assignment 349

9.6 Component Instantiation 352

9.7 Generate Statement 355

10.1 Visibility and Validity Ranges 358

10.2 Use Statements 361

10.3 Design Units and Their Analysis 362

11 Elaboration and Simulation 363

11.1 Elaboration of a Blockheader 363

11.2 Elaboration of a Declaration 365

11.3 Elaboration of a Statement Part 370

11.4 Dynamic Elaboration 373

11.5 Elaboration of a Design Hierarchy 374

11.6 Execution of a Model 375

12 Lexical Elements 379

12.1 Character Set 379

12.2 Delimiters 379

12.3 Identifiers 380

12.4 Abstract Literals 380

12.5 Character Literals 381

12.6 String Literals 381

12.7 Bit String Literals 382

12.9 Reserved Words 383

12.10 Replacing Characters 383

13 Predefined Attributes 384

14 Package STANDARD 393

15 Package TEXTIO 395

16 Bnf 397.

Notes:

Includes bibliographical references and index.

ISBN:

0471899720

OCLC:

43032243