Frequency synthesis by phase lock / William F. Egan.

Format:

Book

Author/Creator:

Egan, William F.

Contributor:

Anne and Joseph Trachtman Memorial Book Fund.

Language:

English

Subjects (All):

Frequency synthesizers.

Phase-locked loops.

Physical Description:

xxviii, 597 pages : illustrations ; 24 cm

Edition:

Second edition.

Place of Publication:

New York : Wiley, [2000]

Summary:

An Instructor Support FTP site is available from the Wiley editorial department.

Contents:

1.1.2 Meaning of Frequency Synthesis 3

1.1.3 Transformation to and from Voltage and Current 3

1.1.4 Units 7

1.2 Mathematical Operations on Frequency 8

1.2.1 Addition and Subtraction: The Mixer 8

1.2.2 Frequency Multipliers 13

1.2.3 Frequency Dividers 13

1.3 Synthesizer Types 14

1.3.1 Direct Digital (Look-Up Table) Synthesizer 15

1.3.2 Direct (Analog) Synthesizer 19

1.3.3 Phase-Locked (Indirect) Synthesizer 24

1.4 Phase-Coherent and Phase-Continuous Switching 27

1.5 Combinations of Techniques 29

2 The Elementary Phase-Locked Synthesizer 35

2.1 Basic Components 35

2.1.1 Voltage-Controlled Oscillator 35

2.1.2 Divide-by-N ([divide] N] 40

2.1.3 Phase Detector 40

2.1.4 Loop Filter 41

2.2 Loop Operation 42

2.2.1 Qualitative Description 42

2.2.2 Mathematical Description 44

2.3 Loop Low-Pass Filter 55

2.4 Hold-In Range 57

2.5 Transient Response 58

2.A Appendix: Linearizer Design 63

2.A.1 Straight-Line Approximation 65

2.A.2 Continuous Approximation 68

3 Modulation, Sidebands, and Noise Spectrums 71

3.1 Spectral Representation of AM and Narrow-Band FM 72

3.2 Decomposition of SSB into AM and FM 75

3.3 Effects of Modulation of the Local Oscillator in a Mixer 78

3.3.1 FM Transfer 78

3.3.2 AM Suppression 78

3.3.3 Mixing Between LO Components 79

3.3.4 Leak-Through 80

3.3.5 Contamination of the IF 80

3.4 Effect of Modulation of a Multiplied Signal 84

3.5 Effect of Modulation of a Divided Signal 87

3.6 Oscillator Spectrums 94

3.6.1 Effect of Internal Noise Sources 94

3.6.2 Effect of External Noise Sources 96

3.6.3 Delay-Line (Ring) Oscillators 99

3.6.4 Relaxation Oscillators 101

3.7 Relationships Between Spectral Densities 102

3.8 Typical Spectral Shapes 106

3.9 Component Noise 114

3.9.1 Passive Components 115

3.9.2 Transistors 119

3.9.3 Relationship Between Phase Noise and Power Consumption 120

3.9.4 Other Active Blocks 121

3.9.5 Operational-Amplifier Noise and the Loop Filter 121

3.9.6 Frequency Dividers 123

3.9.7 Frequency Multipliers 126

3.9.8 Finding Noise Sources 127

3.10 Noise Density at the Syntheizer Output 129

3.A Appendix: The Effect of Vibration on Oscillators 133

3.B Appendix: Considerations of the Upper Integration Limit in Eq. (3.39) 135

4 Frequency Dividers 139

4.1 Flip-Flops 139

4.2 Frequency Divider Types 142

4.3 Presettable Dividers 146

4.4 Prescalers and Pulse Swallowers 153

4.4.1 Increasing the Modulus of a VMP 157

4.4.2 Using Pulse Swallowers in Series 157

4.4.3 Using Three-Modulus VMPs 162

4.4.4 Using Four-Modulus VMPs 162

4.5 Other Bases 162

4.6 Presetting and Offsetting 163

4.7 Other Logic Circuits Used in Synthesizers 166

4.8 Precautions 167

4.9 Interfacing With RF Input and Different Logic Families 168

4.9.1 Gates Biased as Amplifiers 168

4.9.2 Sine- to Square-Wave Conversion 168

4.9.3 Interfacing with ECL 170

5 Phase Detectors 175

5.1 Balanced Mixer 175

5.2 High-Speed Sampler 177

5.3 Exclusive OR 180

5.4 Flip-Flop 182

5.5 Comparing Sideband Levels 187

5.6 Sample-and-Hold Phase Detector 188

5.7 The Charge-Pump Phase Detector 197

5.7.1 Operation of the Charge Pump in the Linear Range 197

5.7.2 Crossover Distortion 203

5.7.3 Filtering the f[subscript ref] Components With an Integrating Filter 214

5.7.4 Filtering the f[subscript ref] Components With a Low-Pass Filter 218

5.7.5 Low-Pass Transfer Function With Approximate Charge Pump 220

5.7.6 Effects of Imbalance in the Charge-Pump Output Pulses 222

5.7.7 Sampling Effects 226

5.8 Computing Phase Digitally 227

5.9 Filter Placement 228

5.10 Sideband Level and Dependence on N 228

5.A Appendix: Edge Triggered J

K Flip-Flop 230

5.B Appendix: Effect of Noise Current into Ramp Capacitor 232

5.C Appendix: Crossover Distortion in Charge-Pump Phase Detectors 233

5.C.1 Comparison and Equivalence of Logic Realizations 233

5.C.2 Claims of Improved Performance 236

5.D Appendix: Transfer Function of Approximate Charge Pump and Low-Pass Filter 240

6 Higher-Order Loops 245

6.1 The General Second-Order Loop 247

6.1.1 Equations 250

6.1.2 Geometric Interpretation 251

6.1.3 Circuit Equivalence 254

6.1.4 Transient Response 256

6.1.5 Slow Response Due to Imbalance 259

6.1.6 Modulation Response 260

6.2 Third-Order Loop 260

6.2.1 Loop with Integrator-plus-Lead

Lag Filter 260

6.2.2 Exact Analysis of a Special Case 267

6.3 A Convenient Second-Order Filter 270

6.4 State-Space Analysis 271

6.4.1 Transfer Functions 271

6.4.2 State Variables 272

6.4.3 Matrix Differential Equation 272

6.4.4 Solution of the Time-Response Equation 273

6.4.5 Computer-Aided Solutions 274

6.4.6 Another Method 275

6.A Appendix: Responses Between Nodes 276

6.B Appendix: Evidence that Type-2 Loops Are Slower 278

6.B.1 Theoretical Considerations 278

6.B.2 Evidence from Simulation 279

6.B.3 Evidence from Computed Results 280

6.M Appendix: Modulation-Response Curves 287

6.T Appendix: Transient-Response Curves 292

7 Sampling Effects 301

7.1 The Sampling Model 301

7.1.1 Sample-and-Hold Phase Detector 302

7.1.2 Charge-Pump Phase Detector 302

7.2 First-Order Correction for Sampling 304

7.2.1 Sample-and-Hold Phase Detector, The Hold 304

7.2.2 Charge-Pump Phase Detector, The Effective Hold 312

7.3 z-Transform Representation 312

7.3.1 Sample-and-Hold Phase Detector 312

7.3.2 Charge-Pump Phase Detector 315

7.3.3 Step Response 320

7.4 Laplace Representation with Sampling 323

7.4.1 Second-Order Loop 328

7.4.2 Third-Order Loop 328

7.4.3 When Are Sampling Effects Important? 329

7.4.4 Effect on Modulation Response 329

7.A Appendix: Obtaining z-Transforms 336

7.B Appendix: Effective Hold 337

7.B.1 Graphical View 338

7.B.2 Mathematical Basis 338

7.S Appendix: Software 340

BdT103.m and BdT103sb.m 340

EvZord3 341

GSmpl 341

Invz 341

8 Architectures 343

8.1 Heterodyning Within the Synthesizer 344

8.1.1 Spurious Coupling to the Output 345

8.1.2 Spurious Coupling to the Loop 345

8.1.3 Miscounts Due to Spurious Signals 347

8.1.4 The Effect of IF Filters 349

8.1.5 Dynamic Range with IF 351

8.2 Architectures Employing Heterodyning 351

8.2.1 Multiply Output Frequency 352

8.2.2 Divide and Sum 353

8.2.3 Offset References 357

8.3 Fractional-N and Relatives 371

8.3.1 The Digiphase Synthesizer 372

8.3.2 Fractional-N Synthesizer 376

8.3.3 Spurious Frequencies with Fractional Division 377

8.3.4 Reduction of Sideband by Digital Processing 379

8.3.5 Multistage Fractional Divider 383

8.4 Other Uses of Pulse Addition and Subtraction 391

8.4.1 High Modulation Index FM of Synthesizer Signal 391

8.4.2 Frequency Offsetting 392

8.A Appendix: Computing Minimum Divide Ratio 393

9 Large-Signal Performance, Natural Acquisition 399

9.1 Simple Loop Acquiring Lock 400

9.1.1 Optimized Gain Shaping 401

9.1.2 Constant Gain 403

9.2 Formulas for Nonlinear Behavior 408

9.2.1 First-Order Loop 410

9.2.2 Second-Order Loop 411

9.3 The Pull-In Process 420

9.4 False Lock Due to Phase Shift 423

9.5 False Lock Due to Sampling 426

9.6 Monitoring Lock 435

9.6.1 Coherent Detector 435

9.6.2 Level Detector 435

9.6.3 Logic 436

9.6.4 Processing the Out-of-Lock Signal 436

9.7 Testing Acquisition 436

9.7.1 Testing Ranges 437

9.7.2 Testing Speed 437

9.A Appendix: Detailed Analysis of Simple Loop Acquiring Lock 441

10 Acquisition Aids 445

10.1 The Frequency Discriminator as an Acquisition Aid 445

10.2 The Search Oscillator as an Acquisition Aid 448

10.3 Changing Loop Parameters to Aid Acquisition 451

10.4 Acquisition-Aiding Logic 451

10.4.1 Charge-Pump

Phase-Frequency Detector 452

10.4.2 Quad-D Phase-Frequency Detector 459

10.4.3 Square-Wave Phase-Frequency Detector 463

10.4.4 Sample and Hold Phase Detector 465

10.4.5 Extended Range 474

10.4.6 Speed-Up Circuits 476

10.4.7 Improved Sine PD 484

10.5 Effect of Sign Reversals in Mixers 484

10.A Appendix: Further Consideration of the Charge-Pump PFD's Out-of-Lock Output 486

10.B Appendix: Comparison of S&H and Charge-Pump PFD 487

11 Spectral Purity 491

11.1 Noise Suppression 491

11.2 Sampling Effects on the Noise Spectrum 493

11.3 Sidebands Caused by Injection Locking 495

11.4 Conversion of Phase-Noise Density to Other Stability Measures 497

11.4.1 Phase and Frequency Deviation 497

11.4.2 Allan Variance 499

11.4.3 Calculations of Other Time-Domain Stability Measures 503

11.4.4 Jitter 504

11.4.5 Units in This Section 506

11.5 Measurement of Frequency Stability 507

11.5.1 Measurement with a Phase Detector 507

11.5.2 Measurement with a Frequency Discriminator 509

11.5.3 Measurement of Sideband Density 511

12 Computer-Aided Engineering 515

12.1 Frequency-Domain Analysis 515

12.1.1 Stability Analysis 515

12.1.2 Modulation Response 518

12.2 Time-Domain Analysis 519

12.2.1 Response with z-Transforms 519

12.2.2 Nonlinear Simulation 519

12.2.3 S&H PD, Using State-Space Method 521

12.2.4 Charge Pump PFD, Using State-Space Method 530

12.2.5 Approximate Solution with State-Space Variables 538

12.2.6 Simulation Without State Space 538

12.3 Synthesizer CAE Programs 541

12.3.1 Open- and Closed-Loop Responses 547

12.3.2 Noise Levels 547

12.3.3 Transient Response 556

12.3.4 Computation Methods and Accuracy 561

12.3.5 Comparison of Program Types 563

12.3.6 Simple Tests for Synthesizer Software 564

12.A Appendix: Using the Matrix Inverse to Set Initial Values 565.

Notes:

Includes bibliographical references (pages 569-579) and index.

Local Notes:

Acquired for the Penn Libraries with assistance from the Anne and Joseph Trachtman Memorial Book Fund.

ISBN:

0471321044

OCLC:

40996234