A new fast 2-D DCT/IDCT algorithm and its VLSI implementation / Feng Pan.

Format:

Book

Manuscript

Microformat

Thesis/Dissertation

Author/Creator:

Pan, Feng.

Contributor:

El Zarki, Magda, advisor.

Sørensen, Henrik, advisor.

University of Pennsylvania.

Language:

English

Subjects (All):

Penn dissertations--Electrical engineering.

Electrical engineering--Penn dissertations.

Local Subjects:

Penn dissertations--Electrical engineering.

Electrical engineering--Penn dissertations.

Physical Description:

xi, 134 pages : illustrations ; 29 cm

Production:

1997.

Summary:

The 2-D Discrete Cosine Transform and Inverse Discrete Cosine Transform (DCT/IDCT) have been widely used in the image and video compression. They are the kernel components of MPEG-1 and MPEG-2 video compression standards. In general, all the existing 2-D DCT/IDCT fast algorithms can be classified as computing DCT/IDCT via other transforms, via direct matrix factorization/decomposition, and via row-column decomposition method. For VLSI implementation of any fast 2-D DCT/IDCT algorithm, regularity of design, localized interconnection and feasibility of layout seem to be the primary concern, which make the algorithms computing 2-D DCT/IDCT via row-column decomposition method so far the only candidates suitable for hardware implementation, even though this approach is not as computation efficient as the other two, usually requires memory components and complex transposition mechanics, and has relatively low data throughput.

In order to meet the high DCT/IDCT throughput requirement of HDTV, a novel 2-D DCT/IDCT algorithm is proposed in this work. Based on the direct 2-D matrix factorization approach, the DCT/IDCT algorithm is not only computation efficient and requires a smaller number of multiplications, but also has paralleled structure and localized interconnections. Besides, much shorter finite internal wordlength is required by the algorithm to meet H.261 and JPEG's DCT/IDCT accuracy requirements. All above features make this algorithm a perfect candidate for VLSI implementation.

Furthermore, modern synthesis-oriented ASIC design approach is adopted to the VLSI implementation of the proposed 2-D DCT/IDCT algorithm. By coding the algorithm with Verilog Hardware Description Language (HDL), the simulation and verification of circuit functionalities and timing characters are easily determined using Cadence's Verilog-XL$\sp{\circler}$ simulation tool. The logic synthesis of the validated RTL codes is also carried out using Synopsys Design Compiler$\sp{\circler}$ EDA tool. Based on 3.3v 0.35$\mu$m CMOS technology, the synthesized 2-D DCT/IDCT module is constructed with concurrent pipelined architecture and consists of only adders and subtractors as processing elements. With estimated 6.84 mm$\sp2$ die size, 800 Msamples/s high throughput with only a few cycles circuit latency can be achieved for both 2-D DCT and IDCT operations, which make it be able to meet any current or near future HDTV DCT/IDCT requirements.

Notes:

Supervisors: Magda El Zarki; Henrik Sorensen.

Thesis (Ph.D. in Electrical Engineering) -- University of Pennsylvania, 1997.

Includes bibliographical references and index.

Local Notes:

University Microfilms order no.: 98-14900.

OCLC:

187457386