A level-crossing sampling scheme for A/D conversion / Necip Sayiner.

Format:

Book

Manuscript

Microformat

Thesis/Dissertation

Author/Creator:

Sayiner, Necip.

Contributor:

Sorenson, Henrik, advisor.

University of Pennsylvania.

Language:

English

Subjects (All):

Penn dissertations--Electrical engineering.

Electrical engineering--Penn dissertations.

Local Subjects:

Penn dissertations--Electrical engineering.

Electrical engineering--Penn dissertations.

Physical Description:

x, 118 leaves : illustrations ; 29 cm

Production:

1994.

Summary:

There is an inherent trade-off between the requirements for the bandwidth and the dynamic range to obtain a desired resolution with an A/D converter. Nyquist sampling requires the smallest bandwidth, but a large number of quantization levels are needed to achieve high resolution. At the other extreme, a signal can be represented in terms of the instants in which the signal assumes a prespecified value, a strategy often referred to as zero-crossing. In this thesis, a novel generalized sampling scheme (with Nyquist sampling and zero-crossing representations being special cases) which is based on multiple level-crossings is presented. The sampling strategy consists of having a number of fixed quantization levels and recording the time instants at which the input signal crosses any of these levels. The mean quantization error for different classes of signals are analyzed. An architecture for an A/D converter that utilizes this sampling scheme is developed. Each stage of the architecture is investigated and its properties are described. The trade-offs regarding the characteristics of each stage are discussed and the simulation results pertaining to the trade-offs are presented. General guidelines in determining a set of parameters (including the number of quantization levels, the linearity of these levels and the clock rate) for a desired level of performance are stated. There are major benefits of this scheme in the VLSI implementation. The analog circuitry required is much simpler than that of a traditional A/D converter. This brings reduction in the chip area and the power consumption. Comparisons of the proposed scheme with other oversampling schemes are made. A novel implementation of the A/D converter is described. A prototype chip based on these ideas is designed and produced. The functional blocks are described in detail, emphasizing the criteria that affect the overall performance. Experimental results with the prototype chip are presented and are related to the predictions of the analyses and software simulation results.

Notes:

Supervisor: Henrik Sorenson.

Thesis (Ph.D. in Electrical Engineering) -- Graduate School of Arts and Sciences, University of Pennsylvania, 1994.

Includes bibliographical references and index.

Local Notes:

University Microfilms order no.: 95-03825.

OCLC:

187466796